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* Revert "DebugInfo: Move type units into the debug_types section with ↵David Blaikie2013-12-114-57/+9
| | | | | | | | | | | | appropriate comdat grouping and type unit headers" This reverts commit r197073. The test seems to be failing on some buildbots for unknown reasons. Reverting until I can figure that out. If anyone's got a reproduction (.s and .o together would be great) - I'd really appreciate it. llvm-svn: 197079
* DebugInfo: Move type units into the debug_types section with appropriate ↵David Blaikie2013-12-114-9/+57
| | | | | | | | | | | comdat grouping and type unit headers This commit does not complete the type units feature - there are issues around fission support (skeletal type units, pubtypes/pubnames) and hashing of some types including those containing references to types in other type units. llvm-svn: 197073
* DwarfUnit: LLVM_OVERRIDE and constify some functionsDavid Blaikie2013-12-112-4/+4
| | | | llvm-svn: 197072
* [AArch64] Add NEON scalar floating-point compare LLVM AArch64 intrinsics thatChad Rosier2013-12-111-16/+18
| | | | | | use f32/f64 types, rather than their vector equivalents. llvm-svn: 197068
* [AArch64] Refactor the NEON scalar floating-point reciprocal step andChad Rosier2013-12-111-11/+11
| | | | | | | floating-point reciprocal square root step LLVM AArch64 intrinsics to use f32/f64 types, rather than their vector equivalents. llvm-svn: 197067
* [AArch64] Refactor the NEON scalar floating-point reciprocal estimate, floating-Chad Rosier2013-12-111-10/+19
| | | | | | | | point reciprocal exponent, and floating-point reciprocal square root estimate LLVM AArch64 intrinsics to use f32/f64 types, rather than their vector equivalents. llvm-svn: 197066
* Don't set unused variable.Rafael Espindola2013-12-111-1/+0
| | | | llvm-svn: 197064
* R600: Re-format Processors.tdTom Stellard2013-12-111-0/+48
| | | | | | | This makes it a little easier to read. Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 197058
* R600: Register AMDGPUCFGStructurizer passTom Stellard2013-12-113-10/+23
| | | | | | | This enables -print-before-all to dump MachineInstrs after it is run. Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 197057
* R600: Register R600EmitClauseMarkers passTom Stellard2013-12-113-9/+19
| | | | | | | This enables -print-before-all to dump MachineInstrs after it is run. Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 197056
* [arm] Implement ARM .arch directive.Logan Chien2013-12-114-2/+223
| | | | llvm-svn: 197052
* SelectionDAG: Fix a typo.Benjamin Kramer2013-12-111-1/+1
| | | | | | Found by "cppcheck". PR18208. llvm-svn: 197047
* ARM: constrain register-class in fast-iselTim Northover2013-12-111-1/+3
| | | | | | | | The tests were no longer using fast-isel at all (MachO needs an "ios" rather than "darwin" triple at the moment and Linux needs ARM mode). Once that was corrected, the verifier complained about a t2ADDri created for the alloca. llvm-svn: 197046
* Build fix for Android NDK which has neither futimes nor futimensAlp Toker2013-12-111-3/+6
| | | | | | Based on a patch by Neil Henning! llvm-svn: 197045
* AVX-512: Removed "z" suffix from AVX-512 instructions, since it is ↵Elena Demikhovsky2013-12-112-99/+102
| | | | | | | | | incompatible with GCC. I moved a test from avx512-vbroadcast-crash.ll to avx512-vbroadcast.ll I defined HasAVX512 predicate as AssemblerPredicate. It means that you should invoke llvm-mc with "-mcpu=knl" to get encoding for AVX-512 instructions. I need this to let AsmMatcher to set different encoding for AVX and AVX-512 instructions that have the same mnemonic and operands (all scalar instructions). llvm-svn: 197041
* [SystemZ] Optimize fcmp X, 0 in cases where X is also negatedRichard Sandiford2013-12-111-4/+30
| | | | | | | In such cases it's often better to test the result of the negation instead, since the negation also sets CC. llvm-svn: 197032
* Extend (truncate (load)) foldingRichard Sandiford2013-12-111-0/+14
| | | | | | | | | DAGCombiner could fold (truncate (load)) -> smaller load if the original load was the width of the truncation result or wider. This patch extends it to handle cases where the original load was narrower (and so the extension type stays the same). llvm-svn: 197030
* Add TargetRegisterInfo::reverseLocalAssignment hook.Andrew Trick2013-12-111-1/+8
| | | | | | | | | | | | | | This hook reverses the order of assignment for local live ranges. This will generally allocate shorter local live ranges first. For targets with many registers, this could reduce regalloc compile time by a large factor. It should still achieve optimal coloring; however, it can change register eviction decisions. It is disabled by default for two reasons: (1) Top-down allocation is simpler and easier to debug for targets that don't benefit from reversing the order. (2) Bottom-up allocation could result in poor evicition decisions on some targets affecting the performance of compiled code. llvm-svn: 197001
* Distinguish and choose 16 or 32 bit forms of save/restore for Mips16.Reed Kotler2013-12-112-4/+16
| | | | llvm-svn: 196999
* [AArch64 NEON] Get instruction BSL matched to VSELECT.Kevin Qin2013-12-113-24/+17
| | | | llvm-svn: 196998
* Move mips' datalayout computation out of line and add comments.Rafael Espindola2013-12-111-11/+31
| | | | llvm-svn: 196996
* Move Sparc's getDataLayout out of line and add comments.Rafael Espindola2013-12-112-10/+24
| | | | llvm-svn: 196990
* Prune redundant dependencies in LLVMBuild.txt.NAKAMURA Takumi2013-12-1128-28/+28
| | | | llvm-svn: 196988
* Move PPC's getDataLayoutString out of line and document it better.Rafael Espindola2013-12-112-17/+39
| | | | llvm-svn: 196987
* Revert the backend fatal error from r196939Reid Kleckner2013-12-101-6/+0
| | | | | | | | | | | | | | The combination of inline asm, stack realignment, and dynamic allocas turns out to be too common to reject out of hand. ASan inserts empy inline asm fragments and uses aligned allocas. Compiling any trivial function containing a dynamic alloca with ASan is enough to trigger the check. XFAIL the test cases that would be miscompiled and add one that uses the relevant functionality. llvm-svn: 196986
* Refactor the computation of the x86 datalayout.Rafael Espindola2013-12-101-14/+47
| | | | llvm-svn: 196976
* [asan] Fix the coverage.cc test broken by r196939Reid Kleckner2013-12-101-1/+13
| | | | | | | | | | | | | | | | It was failing because ASan was adding all of the following to one function: - dynamic alloca - stack realignment - inline asm This patch avoids making the static alloca dynamic when coverage is used. ASan should probably not be inserting empty inline asm blobs to inhibit duplicate tail elimination. llvm-svn: 196973
* Use llvm_unreachable instead of assert(0)Matt Arsenault2013-12-109-20/+18
| | | | llvm-svn: 196971
* on darwin<10, fallback to .weak_definition (PPC,X86)David Fang2013-12-107-4/+22
| | | | | | .weak_def_can_be_hidden was not yet supported by the system assembler llvm-svn: 196970
* [AArch64] Refactor the NEON floating-point absolute difference LLVM AArch64Chad Rosier2013-12-101-2/+11
| | | | | | intrinsic to use f32/f64 types, rather than their vector equivalents. llvm-svn: 196965
* [AArch64] Refactor the NEON signed/unsigned floating-point convert to ↵Chad Rosier2013-12-101-2/+2
| | | | | | | | fixed-point LLVM AArch64 intrinsics to use f32/f64, rather than their vector equivalents. llvm-svn: 196964
* [AArch64] Overload NEON signed/unsigned floating-point convert to fixed-pointChad Rosier2013-12-101-16/+10
| | | | | | and fixed-point convert to floating-point LLVM AArch64 intrinsics. llvm-svn: 196963
* [AArch64] Overload NEON signed/unsigned integer convert to floating-pointChad Rosier2013-12-101-8/+5
| | | | | | LLVM AArch64 intrinsics. llvm-svn: 196962
* Fix gcc warnings.Matt Arsenault2013-12-101-0/+2
| | | | | | Unused variable and unused typedef in release build. llvm-svn: 196947
* Reland "Fix miscompile of MS inline assembly with stack realignment"Reid Kleckner2013-12-105-18/+36
| | | | | | | | | | | This re-lands commit r196876, which was reverted in r196879. The tests have been fixed to pass on platforms with a stack alignment larger than 4. Update to clang side tests will land shortly. llvm-svn: 196939
* Make Triple's isOSBinFormatXXX functions partition triple-space.Tim Northover2013-12-107-22/+18
| | | | | | | | | | | Most users would be surprised if "isCOFF" and "isMachO" were simultaneously true, unless they'd put the compiler in a box with a gun attached to a photon detector. This makes sure precisely one of the three formats is true for any triple and simplifies some target logic based on that. llvm-svn: 196934
* [AArch64] Refactor the Neon vector/scalar floating-point convert intrinsics soChad Rosier2013-12-101-13/+30
| | | | | | that they use float/double rather than the vector equivalents when appropriate. llvm-svn: 196930
* [AArch64] Refactor the Neon vector/scalar floating-point convert implementation.Chad Rosier2013-12-101-16/+16
| | | | | | Specifically, reuse the ARM intrinsics when possible. llvm-svn: 196926
* Ensure that the backend no longer emits unnecessary vector insert instructionsAndrea Di Biagio2013-12-101-0/+125
| | | | | | | | | | | | | | | | | | | | | | immediately after SSE scalar fp instructions like addss or mulss. Added patterns to select SSE scalar fp arithmetic instructions from a scalar fp operation followed by a blend. For example, given the following code: __m128 foo(__m128 A, __m128 B) { A[0] += B[0]; return A; } previously we generated: addss %xmm0, %xmm1 movss %xmm1, %xmm0 now we generate: addss %xmm1, %xmm0 llvm-svn: 196925
* R600: Fix an infinite loop when trying to reorganize export/tex vector inputVincent Lejeune2013-12-101-5/+8
| | | | llvm-svn: 196923
* R600: Fix input modifiers lost for CaymanVincent Lejeune2013-12-101-0/+18
| | | | llvm-svn: 196922
* Next step in Mips16 prologue/epilogue cleanup.Reed Kotler2013-12-104-18/+56
| | | | | | | | Save S2(reg 18) only when we are calling floating point stubs that have a return value of float or complex. Some more work to make this better but this is the first step. llvm-svn: 196921
* AVX-512: changed intrinsics for mask operationsElena Demikhovsky2013-12-102-16/+28
| | | | llvm-svn: 196918
* AVX-512: Changed intrinsics of VPCONFLICT to match GCC builtin formElena Demikhovsky2013-12-102-19/+39
| | | | llvm-svn: 196914
* Darwin: update default iOS version to 5.0Tim Northover2013-12-101-3/+3
| | | | | | | | | | | | Defaulting to iOS 3.0 when LLVM has to guess the version is no longer a useful option and can give surprising results (like tail calls being disabled). 5.0 seems like a reasonable compromise as a platform that's still interesting to some people. rdar://problem/15567348 llvm-svn: 196912
* [mips][msa] Correct sld and sldi builtins.Daniel Sanders2013-12-101-13/+21
| | | | | | | | | | | | | Summary: The result register of these instructions is also the first operand. Reviewers: jacksprat, dsanders Reviewed By: dsanders Differential Revision: http://llvm-reviews.chandlerc.com/D2362 Differential Revision: http://llvm-reviews.chandlerc.com/D2363 llvm-svn: 196910
* Add TargetLowering::prepareVolatileOrAtomicLoadRichard Sandiford2013-12-103-27/+47
| | | | | | | | | | | | | | | | | One unusual feature of the z architecture is that the result of a previous load can be reused indefinitely for subsequent loads, even if a cache-coherent store to that location is performed by another CPU. A special serializing instruction must be used if you want to force a load to be reattempted. Since volatile loads are not supposed to be omitted in this way, we should insert a serializing instruction before each such load. The same goes for atomic loads. The patch implements this at the IR->DAG boundary, in a similar way to atomic fences. It is a no-op for targets other than SystemZ. llvm-svn: 196906
* Add TargetLowering::prepareVolatileOrAtomicLoadRichard Sandiford2013-12-109-4/+45
| | | | | | | | | | | | | | | | | One unusual feature of the z architecture is that the result of a previous load can be reused indefinitely for subsequent loads, even if a cache-coherent store to that location is performed by another CPU. A special serializing instruction must be used if you want to force a load to be reattempted. Since volatile loads are not supposed to be omitted in this way, we should insert a serializing instruction before each such load. The same goes for atomic loads. The patch implements this at the IR->DAG boundary, in a similar way to atomic fences. It is a no-op for targets other than SystemZ. llvm-svn: 196905
* [AArch64 NEON] Replace fpimm with fpz32 for floating compare with zero.Kevin Qin2013-12-101-3/+3
| | | | | | This is a small change to be strict. Just want get pattern safer. llvm-svn: 196889
* [AArch64 NEON] Support poly128_t and implement relevant intrinsic.Kevin Qin2013-12-101-11/+18
| | | | llvm-svn: 196887
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