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* [NFC] Introduce a 'struct Range' for IRCESanjoy Das2015-01-221-17/+27
| | | | | | | | | Use the struct instead of a std::pair<Value *, Value *>. This makes a Range an obviously immutable object, and we can now assert that a range is well-typed (Begin->getType() == End->getType()) on its construction. llvm-svn: 226804
* Revert r226798. Guess I missed the patterns.Craig Topper2015-01-221-2/+2
| | | | llvm-svn: 226802
* Use u8imm instead of i32i8imm on a couple instructions that have no patterns ↵Craig Topper2015-01-221-2/+2
| | | | | | and thus no reason to use a larger operand size. llvm-svn: 226798
* [X86] Remove some unused multiclasses from AVX512 instruction file.Craig Topper2015-01-221-101/+0
| | | | llvm-svn: 226797
* Fix crashes in IRCE caused by mismatched typesSanjoy Das2015-01-221-7/+35
| | | | | | | | | | | | | | | There are places where the inductive range check elimination pass depends on two llvm::Values or llvm::SCEVs to be of the same llvm::Type when they do not need to be. This patch relaxes those restrictions (by bailing out of the optimization if the types mismatch), and adds test cases to trigger those paths. These issues were found by bootstrapping clang with IRCE running in the -O3 pass ordering. Differential Revision: http://reviews.llvm.org/D7082 llvm-svn: 226793
* SLPVectorizer: add a second limit for the number of alias checks.Erik Eckstein2015-01-221-21/+49
| | | | | | | | Even with the current limit on the number of alias checks, the containing loop has quadratic complexity. This begins to hurt for blocks containing > 1K load/store instructions. This commit introduces a limit for the loop count. It reduces the runtime for such very large blocks. llvm-svn: 226792
* Fixed a bug in masked load/store in reversed loop.Elena Demikhovsky2015-01-221-0/+2
| | | | | | | | | Added a test. The bug was submitted to bugzilla: http://llvm.org/bugs/show_bug.cgi?id=22225 llvm-svn: 226791
* [PM] Rename InstCombine.h to InstCombineInternal.h in preparation forChandler Carruth2015-01-2214-16/+21
| | | | | | | | | | | | | | | | creating a non-internal header file for the InstCombine pass. I thought about calling this InstCombiner.h or in some way more clearly associating it with the InstCombiner clas that it is primarily defining, but there are several other utility interfaces defined within this for InstCombine. If, in the course of refactoring, those end up moving elsewhere or going away, it might make more sense to make this the combiner's header alone. Naturally, this is a bikeshed to a certain degree, so feel free to lobby for a different shade of paint if this name just doesn't suit you. llvm-svn: 226783
* [canonicalize] Teach InstCombine to canonicalize loads which are onlyChandler Carruth2015-01-221-0/+29
| | | | | | | | | | | | | | | | | | | | | | | ever stored to always use a legal integer type if one is available. Regardless of whether this particular type is good or bad, it ensures we don't get weird differences in generated code (and resulting performance) from "equivalent" patterns that happen to end up using a slightly different type. After some discussion on llvmdev it seems everyone generally likes this canonicalization. However, there may be some parts of LLVM that handle it poorly and need to be fixed. I have at least verified that this doesn't impede GVN and instcombine's store-to-load forwarding powers in any obvious cases. Subtle cases are exactly what we need te flush out if they remain. Also note that this IR pattern should already be hitting LLVM from Clang at least because it is exactly the IR which would be produced if you used memcpy to copy a pointer or floating point between memory instead of a variable. llvm-svn: 226781
* ARM: fail less catastrophically on invalid Windows inputSaleem Abdulrasool2015-01-223-7/+18
| | | | | | | | | | | | Windows supports a restricted set of relocations (compared to ARM ELF). In some cases, we may end up generating an unsupported relocation. This can occur with bad input to the assembler in particular (the frontend should never generate code that cannot be compiled). Generate an error rather than just aborting. The change in the API is driven by the desire to provide a slightly more helpful message for debugging purposes. llvm-svn: 226779
* [canonicalize] Move a helper function further up the file so it can beChandler Carruth2015-01-221-47/+47
| | | | | | used earlier. NFC. llvm-svn: 226777
* Win64 SEH: Emit the constant 1 for catch-all into xdataReid Kleckner2015-01-221-2/+2
| | | | llvm-svn: 226767
* Make ScalarEvolution less aggressive with respect to no-wrap flags.Sanjoy Das2015-01-221-8/+7
| | | | | | | | | | | | ScalarEvolution currently lowers a subtraction recurrence to an add recurrence with the same no-wrap flags as the subtraction. This is incorrect because `sub nsw X, Y` is not the same as `add nsw X, -Y` and `sub nuw X, Y` is not the same as `add nuw X, -Y`. This patch fixes the issue, and adds two test cases demonstrating the bug. Differential Revision: http://reviews.llvm.org/D7081 llvm-svn: 226755
* Make DwarfExpression use the new DIExpressionIterator. NFC.Adrian Prantl2015-01-222-30/+36
| | | | llvm-svn: 226748
* Rewrite DIExpression::Verify() using an iterator. NFC.Adrian Prantl2015-01-221-15/+23
| | | | | | Addresses review comments for r226627. llvm-svn: 226747
* [canonicalization] Refactor how we create new stores into a helperChandler Carruth2015-01-211-38/+48
| | | | | | | function. This is a bit tidier anyways and will make a subsquent patch simpler as I want to add another case to this combine. llvm-svn: 226746
* [X86][SSE] Missing SSE/AVX1 memory folding integer instructionsSimon Pilgrim2015-01-211-1/+57
| | | | | | | | | | Added most of the missing integer vector folding patterns for SSE (to SSE42) and AVX1. The most useful of these are probably the i32/i64 extraction, i8/i16/i32/i64 insertions, zero/sign extension, unsigned saturation subtractions, i64 subtractions and the variable mask blends (pblendvb) - others include CLMUL, SSE42 string comparisons and bit tests. Differential Revision: http://reviews.llvm.org/D7094 llvm-svn: 226745
* DAGCombine: fold (or (and X, M), (and X, N)) -> (and X, (or M, N))Tim Northover2015-01-211-0/+11
| | | | | | | It can help with argument juggling on some targets, and is generally a good idea. llvm-svn: 226740
* DebugInfo: Use distinct inlinedAt MDLocations to avoid separate inlined ↵David Blaikie2015-01-211-13/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | calls being coalesced When two calls from the same MDLocation are inlined they currently get treated as one inlined function call (creating difficulty debugging, duplicate variables, etc). Clang worked around this by including column information on inline calls which doesn't address LTO inlining or calls to the same function from the same line and column (such as through a macro). It also didn't address ctor and member function calls. By making the inlinedAt locations distinct, every call site has an explicitly distinct location that cannot be coalesced with any other call. This can produce linearly (2x in the worst case where every call is inlined and the call instruction has a non-call instruction at the same location) more debug locations. Any increase beyond that are in cases where the Clang workaround was insufficient and the new scheme is creating necessary distinct nodes that were being erroneously coalesced previously. After this change to LLVM the incomplete workarounds in Clang. That should reduce the number of debug locations (in a build without column info, the default on Darwin, not the default on Linux) by not creating pseudo-distinct locations for every call to an inline function. (oh, and I made the inlined-at chain rebuilding iterative instead of recursive because I was having trouble wrapping my head around it the way it was - open to discussion on the right design for that function (including going back to a recursive solution)) llvm-svn: 226736
* LiveIntervalAnalysis: Mark subregister defs as undef when we determined they ↵Matthias Braun2015-01-212-5/+24
| | | | | | | | | are only reading a dead superregister value This was not necessary before as this case can only be detected when the liveness analysis is at subregister level. llvm-svn: 226733
* Adding a new cl::HideUnrelatedOptions API to allow clang to migrate off ↵Chris Bieneman2015-01-211-1/+11
| | | | | | | | | | | | | | | | cl::getRegisteredOptions. Summary: cl::getRegisteredOptions really exposes some of the innards of how command line parsing is implemented. Exposing new APIs that allow us to disentangle client code from implementation details will allow us to make more extensive changes to command line parsing. Reviewers: chandlerc, dexonsmith, beanz Reviewed By: dexonsmith Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7100 llvm-svn: 226729
* [X86][SSE] Added support for SSE3 lane duplication shuffle instructionsSimon Pilgrim2015-01-212-25/+37
| | | | | | | | | | | | This patch adds shuffle matching for the SSE3 MOVDDUP, MOVSLDUP and MOVSHDUP instructions. The big use of these being that they avoid many single source shuffles from needing to use (pre-AVX) dual source instructions such as SHUFPD/SHUFPS: causing extra moves and preventing load folds. Adding these instructions uncovered an issue in XFormVExtractWithShuffleIntoLoad which crashed on single operand shuffle instructions (now fixed). It also involved fixing getTargetShuffleMask to correctly identify theses instructions as unary shuffles. Also adds a missing tablegen pattern for MOVDDUP. Differential Revision: http://reviews.llvm.org/D7042 llvm-svn: 226716
* Fix load-store optimizer on thumbv4tJonathan Roelofs2015-01-211-3/+14
| | | | | | | | | | Thumbv4t does not have lo->lo copies other than MOVS, and that can't be predicated. So emit MOVS when needed and bail if there's a predicate. http://reviews.llvm.org/D6592 llvm-svn: 226711
* InstCombine: Don't strip bitcasts off of callsites marked 'thunk'David Majnemer2015-01-211-0/+4
| | | | | | | The return type of a thunk is meaningless, we just want the arguments and return value to be forwarded. llvm-svn: 226708
* [X86][SSE] movddup shuffle mask decodesSimon Pilgrim2015-01-213-18/+52
| | | | | | Patch to provide shuffle decodes and asm comments for the SSE3/AVX1 movddup double duplication instructions. llvm-svn: 226705
* LiveIntervalAnalysis: Factor out code to update liveness on vreg def removalMatthias Braun2015-01-214-53/+41
| | | | | | | | | | | This cleans up code and is more in line with the general philosophy of modifying LiveIntervals through LiveIntervalAnalysis instead of changing them directly. This also fixes a case where SplitEditor::removeBackCopies() would miss the subregister ranges. llvm-svn: 226690
* LiveIntervalAnalysis: Factor out code to update liveness on physreg def removalMatthias Braun2015-01-214-25/+17
| | | | | | | | This cleans up code and is more in line with the general philosophy of modifying LiveIntervals through LiveIntervalAnalysis instead of changing them directly. llvm-svn: 226687
* LiveIntervalAnalysis: Remove unused pruneValue() variant.Matthias Braun2015-01-211-9/+0
| | | | llvm-svn: 226686
* Let subprograms with instructions without parent scopes fail theAdrian Prantl2015-01-211-1/+2
| | | | | | | | verification. Tested via a unit test. Follow-up to r226616. llvm-svn: 226684
* R600/SI: Custom lower froundMatt Arsenault2015-01-214-24/+117
| | | | | | | | | This fixes it for SI. It also removes the pattern used previously for Evergreen for f32. I'm not sure if the the new R600 output is better or not, but it uses 1 fewer instructions if BFI is available. llvm-svn: 226682
* [Hexagon] Converting multiply and accumulate with immediate intrinsics to ↵Colin LeMahieu2015-01-211-0/+21
| | | | | | patterns. llvm-svn: 226681
* [X86] Declare SSE4.1/AVX2 vector extloads covered by PMOV[SZ]X legal.Ahmed Bougacha2015-01-212-9/+70
| | | | | | | | | | | | | | | | | | Now that we can fully specify extload legality, we can declare them legal for the PMOVSX/PMOVZX instructions. This for instance enables a DAGCombine to fire on code such as (and (<zextload-equivalent> ...), <redundant mask>) to turn it into: (zextload ...) as seen in the testcase changes. There is one regression, in widen_load-2.ll: we're no longer able to do store-to-load forwarding with illegal extload memory types. This will be addressed separately. Differential Revision: http://reviews.llvm.org/D6533 llvm-svn: 226676
* Fixed a bug with how we determine bitset indices.George Burgess IV2015-01-211-1/+1
| | | | llvm-svn: 226671
* Add missing include guards to WindowsSupport.h.Yaron Keren2015-01-211-0/+5
| | | | llvm-svn: 226669
* Revert "DAGCombine: fold (or (and X, M), (and X, N)) -> (and X, (or M, N))"Tim Northover2015-01-211-11/+0
| | | | | | | | It hadn't gone through review yet, but was still on my local copy. This reverts commit r226663 llvm-svn: 226665
* AArch64: add backend option to reserve x18 (platform register)Tim Northover2015-01-211-3/+7
| | | | | | | | | AAPCS64 says that it's up to the platform to specify whether x18 is reserved, and a first step on that way is to add a flag controlling it. From: Andrew Turner <andrew@fubar.geek.nz> llvm-svn: 226664
* DAGCombine: fold (or (and X, M), (and X, N)) -> (and X, (or M, N))Tim Northover2015-01-211-0/+11
| | | | llvm-svn: 226663
* [x32] Fast ISel should use LEA64_32r instead of LEA32r to adjust addresses ↵Michael Kuperstein2015-01-211-2/+8
| | | | | | in x32 mode. llvm-svn: 226661
* [msan] Update origin for the entire destination range on memory store.Evgeniy Stepanov2015-01-211-9/+49
| | | | | | | | | Previously we always stored 4 bytes of origin at the destination address even for 8-byte (and longer) stores. This should fix rare missing, or incorrect, origin stacks in MSan reports. llvm-svn: 226658
* [mips][microMIPS] MicroMIPS 16-bit unconditional branch instruction BJozef Kolek2015-01-2111-1/+153
| | | | | | | | | | | | | | Implement microMIPS 16-bit unconditional branch instruction B. Implemented 16-bit microMIPS unconditional instruction has real name B16, and B is an alias which expands to either B16 or BEQ according to the rules: b 256 --> b16 256 # R_MICROMIPS_PC10_S1 b 12256 --> beq $zero, $zero, 12256 # R_MICROMIPS_PC16_S1 b label --> beq $zero, $zero, label # R_MICROMIPS_PC16_S1 Differential Revision: http://reviews.llvm.org/D3514 llvm-svn: 226657
* [mips][microMIPS] Implement ADDIUPC instructionJozef Kolek2015-01-216-0/+56
| | | | | | Differential Revision: http://reviews.llvm.org/D6582 llvm-svn: 226656
* [PM] Refactor the InstCombiner interface to use an external worklist.Chandler Carruth2015-01-212-211/+222
| | | | | | | | | | | | | | | | | | | | | | | | | Because in its primary function pass the combiner is run repeatedly over the same function until doing so produces no changes, it is essentially to not re-allocate the worklist. However, as a utility, the more common pattern would be to put a limited set of instructions in the worklist rather than the entire function body. That is also the more likely pattern when used by the new pass manager. The result is a very light weight combiner that does the visiting with a separable worklist. This can then be wrapped up in a helper function for users that want a combiner utility, or as I have here it can be wrapped up in a pass which manages the iterations used when combining an entire function's instructions. Hopefully this removes some of the worst of the interface warts that became apparant with the last patch here. However, there is clearly more work. I've again left some FIXMEs for the most egregious. The ones that stick out to me are the exposure of the worklist and IR builder as public members, and the use of pointers rather than references. However, fixing these is likely to be much more mechanical and less interesting so I didn't want to touch them in this patch. llvm-svn: 226655
* [PM] Simplify (ha! ha!) the way that instcombine calls theChandler Carruth2015-01-213-9/+6
| | | | | | | | | | | | SimplifyLibCalls utility by sinking it into the specific call part of the combiner. This will avoid us needing to do any contortions to build this object in a subsequent refactoring I'm doing and seems generally better factored. We don't need this utility everywhere and it carries no interesting state so we might as well build it on demand. llvm-svn: 226654
* [Mips][Disassembler]When disassembler meets load/store from coprocessor 2 ↵Vladimir Medic2015-01-212-0/+23
| | | | | | instructions for mips r6 it crashes as the access to operands array is out of range. This patch adds dedicated decoder method that properly handles decoding of these instructions. llvm-svn: 226652
* [x86] Remove some unnecessary and slightly confusing typecasts from some ↵Craig Topper2015-01-211-4/+4
| | | | | | patterns. I think it actually went i32->iPtr->i32 in some of these cases. llvm-svn: 226647
* [X86] Convert all the i8imm used by AVX512 and MMX instructions to u8imm.Craig Topper2015-01-212-27/+27
| | | | llvm-svn: 226646
* [X86] Convert all the i8imm used by SSE and AVX instructions to u8imm.Craig Topper2015-01-213-77/+66
| | | | | | This makes the assembler check their size and removes a hack from the disassembler to avoid sign extending the immediate. llvm-svn: 226645
* [x86] Add assembly parser bounds checking to the immediate value for ↵Craig Topper2015-01-215-14/+40
| | | | | | cmpss/cmpsd/cmpps/cmppd. llvm-svn: 226642
* [PM] Replace an abuse of inheritance to override a single function withChandler Carruth2015-01-212-27/+15
| | | | | | | | | | | | | a more direct approach: a type-erased glorified function pointer. Now we can pass a function pointer into this for the easy case and we can even pass a lambda into it in the interesting case in the instruction combiner. I'll be using this shortly to simplify the interfaces to InstCombiner, but this helps pave the way and seems like a better design for the libcall simplifier utility. llvm-svn: 226640
* Make DIExpression::Verify() stricter by checking that the number ofAdrian Prantl2015-01-212-9/+36
| | | | | | elements and the ordering is sane and cleanup the accessors. llvm-svn: 226627
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