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* AMDGPU: Fold immediate offset into BUFFER_LOAD_DWORD lowered from SMEMMarek Olsak2017-11-093-14/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: -5.3% code size in affected shaders. Changed stats only: 48486 shaders in 30489 tests Totals: SGPRS: 2086406 -> 2072430 (-0.67 %) VGPRS: 1626872 -> 1627960 (0.07 %) Spilled SGPRs: 7865 -> 7912 (0.60 %) Code Size: 60978060 -> 60188764 (-1.29 %) bytes Max Waves: 374530 -> 374342 (-0.05 %) Totals from affected shaders: SGPRS: 299664 -> 285688 (-4.66 %) VGPRS: 233844 -> 234932 (0.47 %) Spilled SGPRs: 3959 -> 4006 (1.19 %) Code Size: 14905272 -> 14115976 (-5.30 %) bytes Max Waves: 46202 -> 46014 (-0.41 %) Reviewers: arsenm, nhaehnle Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D38915 llvm-svn: 317750
* [X86] Make sure we don't read too many operands from X86ISD::FMADDS1/FMADDS3 ↵Craig Topper2017-11-091-2/+5
| | | | | | | | nodes when doing FNEG combine. r317453 added new ISD nodes without rounding modes that were added to an existing if/else chain. But all the previous nodes handled there included a rounding mode. The final code after this if/else chain expected an extra operand that isn't present for the new nodes. llvm-svn: 317748
* [FileOutputBuffer] Move factory methods out of their classes.Rui Ueyama2017-11-081-17/+14
| | | | | | | | | | InMemoryBuffer and OnDiskBuffer classes have both factory methods and public constructors, and that looks a bit odd. This patch makes factory methods non-member function to fix it. Differential Revision: https://reviews.llvm.org/D39693 llvm-svn: 317739
* [X86] X86MaskedGatherSDNode shouldn't inherit from MaskedGatherScatterSDNodeCraig Topper2017-11-081-2/+10
| | | | | | The classof implementation in MaskedGatherScatterSDNode doesn't consider X86MaskedGatherSDNode so its misleading. llvm-svn: 317733
* [X86] Preserve memory refs when folding loads into divides.Craig Topper2017-11-081-1/+5
| | | | | | This is similar to what we already do for multiplies. Without this we can't unfold and hoist an invariant load. llvm-svn: 317732
* [X86] Remove an if check on the result of a cast. NFCCraig Topper2017-11-081-12/+6
| | | | | | cast takes a non-null input and produces a non-null output. So this if can never fail. llvm-svn: 317731
* Let replaceVTableHolder accept any type.Adrian Prantl2017-11-082-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | In Rust, a trait can be implemented for any type, and if a trait object pointer is used for the type, then a virtual table will be emitted for that trait/type combination. We would like debuggers to be able to inspect trait objects, which requires finding the concrete type associated with a given vtable. This patch changes LLVM so that any type can be passed to replaceVTableHolder. This allows the Rust compiler to emit the needed debug info -- associating a vtable with the concrete type for which it was emitted. This is a DWARF extension: DWARF only specifies the meaning of DW_AT_containing_type in one specific situation. This style of DWARF extension is routine, though, and LLVM already has one such case for DW_AT_containing_type. Patch by Tom Tromey! Differential Revision: https://reviews.llvm.org/D39503 llvm-svn: 317730
* Add an @llvm.sideeffect intrinsicDan Gohman2017-11-0811-6/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch implements Chandler's idea [0] for supporting languages that require support for infinite loops with side effects, such as Rust, providing part of a solution to bug 965 [1]. Specifically, it adds an `llvm.sideeffect()` intrinsic, which has no actual effect, but which appears to optimization passes to have obscure side effects, such that they don't optimize away loops containing it. It also teaches several optimization passes to ignore this intrinsic, so that it doesn't significantly impact optimization in most cases. As discussed on llvm-dev [2], this patch is the first of two major parts. The second part, to change LLVM's semantics to have defined behavior on infinite loops by default, with a function attribute for opting into potential-undefined-behavior, will be implemented and posted for review in a separate patch. [0] http://lists.llvm.org/pipermail/llvm-dev/2015-July/088103.html [1] https://bugs.llvm.org/show_bug.cgi?id=965 [2] http://lists.llvm.org/pipermail/llvm-dev/2017-October/118632.html Differential Revision: https://reviews.llvm.org/D38336 llvm-svn: 317729
* Revert "Correct dwarf unwind information in function epilogue for X86"Reid Kleckner2017-11-0810-481/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts r317579, originally committed as r317100. There is a design issue with marking CFI instructions duplicatable. Not all targets support the CFIInstrInserter pass, and targets like Darwin can't cope with duplicated prologue setup CFI instructions. The compact unwind info emission fails. When the following code is compiled for arm64 on Mac at -O3, the CFI instructions end up getting tail duplicated, which causes compact unwind info emission to fail: int a, c, d, e, f, g, h, i, j, k, l, m; void n(int o, int *b) { if (g) f = 0; for (; f < o; f++) { m = a; if (l > j * k > i) j = i = k = d; h = b[c] - e; } } We get assembly that looks like this: ; BB#1: ; %if.then Lloh3: adrp x9, _f@GOTPAGE Lloh4: ldr x9, [x9, _f@GOTPAGEOFF] mov w8, wzr Lloh5: str wzr, [x9] stp x20, x19, [sp, #-16]! ; 8-byte Folded Spill .cfi_def_cfa_offset 16 .cfi_offset w19, -8 .cfi_offset w20, -16 cmp w8, w0 b.lt LBB0_3 b LBB0_7 LBB0_2: ; %entry.if.end_crit_edge Lloh6: adrp x8, _f@GOTPAGE Lloh7: ldr x8, [x8, _f@GOTPAGEOFF] Lloh8: ldr w8, [x8] stp x20, x19, [sp, #-16]! ; 8-byte Folded Spill .cfi_def_cfa_offset 16 .cfi_offset w19, -8 .cfi_offset w20, -16 cmp w8, w0 b.ge LBB0_7 LBB0_3: ; %for.body.lr.ph Note the multiple .cfi_def* directives. Compact unwind info emission can't handle that. llvm-svn: 317726
* Set hasSideEffects=0 for PHI and fix affected passesAlex Bradbury2017-11-082-4/+3
| | | | | | | | | | | | | | Previously, hasSideEffects was ? for TargetOpcode::PHI and would be inferred as 1. D37065 sets the previously inferred properties explicitly. This patch sets hasSideEffects=0 for PHI, as it is for G_PHI. MachineInstr::isSafeToMove has been updated so it still returns false for PHI. Additionally, HexagonBitSimplify relied on a PHI node having the hasUnmodeledSideEffects property. This patch fixes that assumption. Differential Revision: https://reviews.llvm.org/D37097 llvm-svn: 317721
* [X86] Correct the implementation of BEXTR load folding to use the shift as ↵Craig Topper2017-11-081-6/+14
| | | | | | | | | | the parent node and pass a separate root. We were calling tryFoldLoad with the 'and' node was the root and parent node of the load. But the parent of the load should be the shift that proceeds the and. While the and node is correctly the root node. To fix this I had to make tryFoldLoad take a separate use and root input. I've added a convenience version with the old signature to avoid updating the other call sites. llvm-svn: 317720
* [WebAssembly] Update test expectationsSam Clegg2017-11-081-14/+3
| | | | | | | | I believe these were fixed in rL317707 Differential Revision: https://reviews.llvm.org/D39813 llvm-svn: 317718
* [ThinLTO] Ensure sanitizer passes are runTeresa Johnson2017-11-081-0/+3
| | | | | | | | | | | | | | | | | | Summary: In ThinLTO compilation, we exit populateModulePassManager early and were not adding PM extension passes meant to run at the end of the pipeline. This includes sanitizer passes. Add these passes before the early exit. A test will be added to projects/compiler-rt. Reviewers: pcc Subscribers: mehdi_amini, inglorion, llvm-commits Differential Revision: https://reviews.llvm.org/D39565 llvm-svn: 317714
* [X86] Don't call validateInstruction from MatchAndEmitInstruction when ↵Craig Topper2017-11-081-2/+2
| | | | | | | | MatchingInlineAsm is set. The MCInst won't be populated. Without this we can't parse gather instructions in ms inline asm blocks. The validateInstruction function was introduced in r316700 to check gather constraints. llvm-svn: 317713
* [ValueTracking] Use APInt::isNullValue/isOneValue which are more efficient ↵Craig Topper2017-11-081-3/+6
| | | | | | for large APInts. llvm-svn: 317712
* [WebAssembly] Call signExtend to get sign extended registerDan Gohman2017-11-081-1/+1
| | | | | | | | Patch by Jatin Bhateja! Differential Revision: https://reviews.llvm.org/D39529 llvm-svn: 317710
* [WebAssembly] Revise the strategy for inline asm.Dan Gohman2017-11-082-6/+25
| | | | | | | | | | | | | | | | | | | | | | Previously, an "r" constraint would mean the compiler provides a value on WebAssembly's operand stack. This was tricky to use properly, particularly since it isn't possible to declare a new local from within an inline asm string. With this patch, "r" provides the value in a WebAssembly local, and the local index is provided to the inline asm string. This requires inline asm to use get_local and set_local to read the register. This does potentially result in larger code size, however inline asm should hopefully be quite rare in WebAssembly. This also means that the "m" constraint can no longer be supported, as WebAssembly has nothing like a "memory operand" that includes an implicit get_local. This fixes PR34599 for the wasm32-unknown-unknown-wasm target (though not for the ELF target). llvm-svn: 317707
* NFC: Rename MCSafeSEHFragment to MCSymbolIdFragmentAdrian McCarthy2017-11-083-9/+9
| | | | | | | | | | | | | | | Summary: This fragment emits a symbol ID and will be useful for more than just Safe SEH tables (e.g., I plan to re-use it for Control Flow Guard tables). This is simply a rename refactor. Reviewers: rnk Subscribers: llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D39770 llvm-svn: 317703
* Handle inlined variables in SelectionDAGBuilder::EmitFuncArgumentDbgValue().Adrian Prantl2017-11-081-6/+0
| | | | | | | | | | | | | | | | | In 2010 a commit with no testcase and no further explanation explicitly disabled the handling of inlined variables in EmitFuncArgumentDbgValue(). I don't think there is a good reason for this any more and re-enabling this adds debug locations for variables associated with an LLVM function argument in functions that are inlined into the first basic block. The only downside of doing this is that we may insert a DBG_VALUE before the inlined scope, but (1) this could be filtered out later, and (2) LiveDebugValues will not propagate it into subsequent basic blocks if they don't dominate the variable's lexical scope, so this seems like a small price to pay. rdar://problem/26228128 llvm-svn: 317702
* [RISCV] Initial support for function callsAlex Bradbury2017-11-088-4/+186
| | | | | | | | | Note that this is just enough for simple function call examples to generate working code. Support for varargs etc follows in future patches. Differential Revision: https://reviews.llvm.org/D29936 llvm-svn: 317691
* [RISCV] Codegen for conditional branchesAlex Bradbury2017-11-088-4/+118
| | | | | | | | | | | | | | | | | | | | A good portion of this patch is the extra functions that needed to be implemented to support the test case. e.g. storeRegToStackSlot, loadRegFromStackSlot, eliminateFrameIndex. Setting ISD::BR_CC to Expand may appear non-obvious on an architecture with branch+cmp instructions. However, I found it much easier to deal with matching the expanded form. I had to change simm13_lsb0 and simm21_lsb0 to inherit from the Operand<OtherVT> class rather than Operand<i32> in order to keep tablegen happy. This isn't a big deal, but it does seem a shame to lose the uniformity across immediate types when there's not an obvious benefit (I'm hoping a tablegen expert will educate me on what I'm missing here!). Differential Revision: https://reviews.llvm.org/D29935 llvm-svn: 317690
* [RISCV] Codegen support for memory operations on global addressesAlex Bradbury2017-11-085-22/+99
| | | | | | Differential Revision: https://reviews.llvm.org/D39103 llvm-svn: 317688
* [RISCV] Codegen support for memory operationsAlex Bradbury2017-11-084-0/+47
| | | | | | | | | This required the implementation of RISCVTargetInstrInfo::copyPhysReg. Support for lowering global addresses follow in the next patch. Differential Revision: https://reviews.llvm.org/D29934 llvm-svn: 317685
* [RISCV] Codegen support for materializing constantsAlex Bradbury2017-11-081-0/+24
| | | | | | Differential Revision: https://reviews.llvm.org/D39101 llvm-svn: 317684
* [Analysis] Fix merging TBAA tags with different final access typesIvan A. Kosarev2017-11-081-24/+13
| | | | | | | | | | | | | | | | | | | | | There are cases when we have to merge TBAA access tags with the same base access type, but different final access types. For example, accesses to different members of the same structure may be vectorized into a single load or store instruction. Since we currently assume that the tags to merge always share the same final access type, we incorrectly return a tag that describes an access to one of the original final access types as the generic tag. This patch fixes that by producing generic tags for the common type and not the final access types of the original tags. Resolves: PR35225: Wrong tbaa metadata after load store vectorizer due to recent change https://bugs.llvm.org/show_bug.cgi?id=35225 Differential Revision: https://reviews.llvm.org/D39732 llvm-svn: 317682
* [mips] Guard indirect and tailcall pseudo instructions correctly.Simon Dardis2017-11-083-11/+23
| | | | | | | | | | | Previously these pseudo instructions were not guarded by ISA, so their select was dependant on the ordering of the entries in the DAG matcher. Reviewers: atanasyan Differential Revision: https://reviews.llvm.org/D39723 llvm-svn: 317681
* BasicAA: fix bug where we would return partialalias instead of noaliasNuno Lopes2017-11-081-3/+3
| | | | | | | | | | | | | | | My fix is conservative and will make us return may-alias instead. The test case is: check(gep(x, 0), n, gep(x, n), -1) with n == sizeof(x) Here, the first value accesses the whole object, but the second access doesn't access anything. The semantics of -1 is read until the end of the object, which in this case means read nothing. No test case, since isn't trivial to exploit this one, but I've proved it correct. llvm-svn: 317680
* [NFCI] Ensure TargetOpcode::* are compatible with guessInstructionProperties=0Alex Bradbury2017-11-081-3/+1
| | | | | | | | | | | | | | | | | | | rL162640 introduced CodeGenTarget::guessInstructionProperties. If a target sets guessInstructionProperties=0 in its FooInstrInfo, tablegen will error if it has to guess properties from patterns. Unfortunately, guessInstructionProperties=0 can't be used with current upstream LLVM as instructions in the TargetOpcode namespace are always included and sometimes have inferred properties for mayLoad, mayStore, and hasSideEffects. This patch provides the simplest possible fix to this problem, setting default values for these fields in the TargetOpcode scope. There is no intended functional change, as the explicitly set properties should match what was previously inferred. A number of the instructions had hasSideEffects=1 inferred unintentionally. This patch makes it explicit, while future patches (such as D37097) correct the property. Differential Revision: https://reviews.llvm.org/D37065 llvm-svn: 317674
* DAG: Add computeKnownBitsForFrameIndexMatt Arsenault2017-11-082-5/+14
| | | | | | | | | | | | | Some of the AMDGPU stack addressing modes require knowing the sign bit is zero. We used to accomplish this by custom lowering frame indexes, and then putting an AssertZext around a TargetFrameIndex. This required specifically looking for the AssextZext + frame index pattern which was moderately disgusting. The same could probably be accomplished with a target specific node, but would still require special handling of frame indexes. llvm-svn: 317671
* Revert "[CGP] Enable extending scope of optimizeMemoryInst"Serguei Katkov2017-11-081-1/+1
| | | | | | Revert the patch r317665 causing buildbot failures. llvm-svn: 317667
* [CGP] Enable extending scope of optimizeMemoryInstSerguei Katkov2017-11-081-1/+1
| | | | | | | | | | | This patch enables the folding of address computation in memory instruction in case adress is represented by Phi node. The inputs of Phi node might be different in base register. Differential Revision: https://reviews.llvm.org/D36073 llvm-svn: 317665
* [X86] Add patterns to fold EVEX store with EVEX encoded vcvtps2ph ↵Craig Topper2017-11-081-11/+23
| | | | | | instructions. Remove bad pattern that had vf432 vcvtps2ph storing 128-bits. llvm-svn: 317662
* [X86] Allow legacy vcvtps2ph intrinsics to select EVEX encoded instructions. ↵Craig Topper2017-11-082-18/+16
| | | | | | | | Rely on EVEX->VEX to convert back. Missed store folding opportunities will be fixed in a subsequent commit. llvm-svn: 317661
* Convert FileOutputBuffer::commit to Error.Rafael Espindola2017-11-081-5/+5
| | | | llvm-svn: 317656
* Revert "Reapply: Allow yaml2obj to order implicit sections for ELF"Dave Lee2017-11-081-1/+1
| | | | | | This reverts commit r317646. llvm-svn: 317654
* Convert FileOutputBuffer to Expected. NFC.Rafael Espindola2017-11-082-12/+11
| | | | llvm-svn: 317649
* Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layeringDavid Blaikie2017-11-08172-209/+209
| | | | | | | | This header includes CodeGen headers, and is not, itself, included by any Target headers, so move it into CodeGen to match the layering of its implementation. llvm-svn: 317647
* Reapply: Allow yaml2obj to order implicit sections for ELFDave Lee2017-11-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This change allows yaml input to control the order of implicitly added sections (`.symtab`, `.strtab`, `.shstrtab`). The order is controlled by adding a placeholder section of the given name to the Sections field. This change is to support changes in D39582, where it is desirable to control the location of the `.dynsym` section. This reapplied version fixes: 1. use of a function call within an assert 2. failing lld test which has an unnamed section Additionally, one more test to cover the unnamed section failure. Reviewers: compnerd, jakehehrlich Reviewed By: jakehehrlich Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D39749 llvm-svn: 317646
* AMDGPU: Set correct sched model on v_mad_u64_u32Matt Arsenault2017-11-081-0/+2
| | | | llvm-svn: 317645
* Revert rL317618Mitch Phillips2017-11-081-319/+140
| | | | | | | | | | The implemented pass fails and is breaking a large number of unit tests. Example: http://lab.llvm.org:8011/builders/clang-with-lto-ubuntu/builds/5777/steps/build-stage3-compiler/logs/stdio This reverts commit rL317618 llvm-svn: 317641
* Attribute nonlazybind should not affect calls to functions with hidden ↵Sriraman Tallam2017-11-082-9/+11
| | | | | | | | visibility. Differential Revision: https://reviews.llvm.org/D39625 llvm-svn: 317639
* Revert "Allow yaml2obj to order implicit sections for ELF"Dave Lee2017-11-071-1/+1
| | | | | | | | Also, revert "Fix build bots after r317622" This reverts commit r317622, r317626. llvm-svn: 317630
* [NVPTX] Implement __nvvm_atom_add_gen_d builtin.Justin Lebar2017-11-072-0/+14
| | | | | | | | | | | | | | | Summary: This just seems to have been an oversight. We already supported the f64 atomic add with an explicit scope (e.g. "cta"), but not the scopeless version. Reviewers: tra Subscribers: jholewinski, sanjoy, cfe-commits, llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D39638 llvm-svn: 317623
* Allow yaml2obj to order implicit sections for ELFDave Lee2017-11-071-1/+1
| | | | | | | | | | | | | | | | | | | | Summary: This change allows yaml input to control the order of implicitly added sections (`.symtab`, `.strtab`, `.shstrtab`). The order is controlled by adding a placeholder section of the given name to the Sections field. This change is to support changes in D39582, where it is desirable to control the location of the `.dynsym` section. Reviewers: compnerd, jakehehrlich Reviewed By: jakehehrlich Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D39749 llvm-svn: 317622
* [SLPVectorizer] Failure to beneficially vectorize 'copyable' elements in ↵Dinar Temirbulatov2017-11-071-140/+319
| | | | | | | | | | | | | | | | | | | | | | | | | | integer binary ops. Patch tries to improve vectorization of the following code: void add1(int * __restrict dst, const int * __restrict src) { *dst++ = *src++; *dst++ = *src++ + 1; *dst++ = *src++ + 2; *dst++ = *src++ + 3; } Allows to vectorize even if the very first operation is not a binary add, but just a load. Fixed PR34619 and other issues related to previous commit. Reviewers: spatel, mzolotukhin, mkuper, hfinkel, RKSimon, filcab, ABataev Reviewed By: ABataev, RKSimon Subscribers: llvm-commits, RKSimon Differential Revision: https://reviews.llvm.org/D28907 llvm-svn: 317618
* Extend SpecialCaseList to allow users to blame matches on entries in the file.Mitch Phillips2017-11-071-46/+37
| | | | | | | | | | | | | | | | | | | | | Summary: Extends SCL functionality to allow users to find the line number in the file the SCL is built from through SpecialCaseList::inSectionBlame(...). Also removes the need to compile the SCL before use. As the matcher now contains a list of regexes to test against instead of a single regex, the regexes can be individually built on each insertion rather than one large compilation at the end of construction. This change also fixes a bug where blank lines would cause the parser to become out-of-sync with the line number. An error on line `k` was being reported as being on line `k - num_blank_lines_before_k`. Note: This change has a cyclical dependency on D39486. Both these changes must be submitted at the same time to avoid a build breakage. Reviewers: vlad.tsyrklevich Reviewed By: vlad.tsyrklevich Subscribers: kcc, pcc, llvm-commits Differential Revision: https://reviews.llvm.org/D39485 llvm-svn: 317617
* [CodeGenPrepare] Fix typo in comment. NFCCraig Topper2017-11-071-1/+1
| | | | llvm-svn: 317614
* Use new vector insert half-word and byte instructions when we see ↵Graham Yiu2017-11-072-3/+33
| | | | | | | | insertelement on '8 x i16' and '16 x i8' types. Also extended existing lit testcase to cover these cases. Differential Revision: https://reviews.llvm.org/D34630 llvm-svn: 317613
* [DWARFv5] Support DW_FORM_strp in the .debug_line header.Paul Robinson2017-11-076-27/+31
| | | | | | | | Supporting this form in .debug_line.dwo will be done as a follow-up. Differential Revision: https://reviews.llvm.org/D33155 llvm-svn: 317607
* Recommit r317510 "[InstCombine] Pull shifts through a select plus binop with ↵Craig Topper2017-11-071-27/+82
| | | | | | | | | | | | | | | | constant" The hexagon test should be fixed now. Original commit message: This pulls shifts through a select+binop with a constant where the select conditionally executes the binop. We already do this for just the binop, but not with the select. This can allow us to get the select closer to other selects to enable removing one. Differential Revision: https://reviews.llvm.org/D39222 llvm-svn: 317600
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