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| author | Alex Bradbury <asb@lowrisc.org> | 2017-11-08 20:19:16 +0000 |
|---|---|---|
| committer | Alex Bradbury <asb@lowrisc.org> | 2017-11-08 20:19:16 +0000 |
| commit | fa18b9e73cbe20462e8a8ac3fa95df826adc7b3d (patch) | |
| tree | f343d17c0572d9b2f9f0a692558e64734fad06d9 /llvm/lib | |
| parent | 78a770402afd19f69a18161c637df6af05e5815e (diff) | |
| download | bcm5719-llvm-fa18b9e73cbe20462e8a8ac3fa95df826adc7b3d.tar.gz bcm5719-llvm-fa18b9e73cbe20462e8a8ac3fa95df826adc7b3d.zip | |
Set hasSideEffects=0 for PHI and fix affected passes
Previously, hasSideEffects was ? for TargetOpcode::PHI and would be inferred
as 1. D37065 sets the previously inferred properties explicitly. This patch sets
hasSideEffects=0 for PHI, as it is for G_PHI. MachineInstr::isSafeToMove has
been updated so it still returns false for PHI.
Additionally, HexagonBitSimplify relied on a PHI node having the
hasUnmodeledSideEffects property. This patch fixes that assumption.
Differential Revision: https://reviews.llvm.org/D37097
llvm-svn: 317721
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/CodeGen/MachineInstr.cpp | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp | 5 |
2 files changed, 3 insertions, 4 deletions
diff --git a/llvm/lib/CodeGen/MachineInstr.cpp b/llvm/lib/CodeGen/MachineInstr.cpp index 2c81218f8f6..478a92e22fc 100644 --- a/llvm/lib/CodeGen/MachineInstr.cpp +++ b/llvm/lib/CodeGen/MachineInstr.cpp @@ -1686,7 +1686,7 @@ bool MachineInstr::isSafeToMove(AliasAnalysis *AA, bool &SawStore) const { // Treat volatile loads as stores. This is not strictly necessary for // volatiles, but it is required for atomic loads. It is not allowed to move // a load across an atomic load with Ordering > Monotonic. - if (mayStore() || isCall() || + if (mayStore() || isCall() || isPHI() || (mayLoad() && hasOrderedMemoryRef())) { SawStore = true; return false; diff --git a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp index fe709934160..033718039f9 100644 --- a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp +++ b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp @@ -1315,7 +1315,7 @@ bool RedundantInstrElimination::processBlock(MachineBasicBlock &B, if (MI->getOpcode() == TargetOpcode::COPY) continue; - if (MI->hasUnmodeledSideEffects() || MI->isInlineAsm()) + if (MI->isPHI() || MI->hasUnmodeledSideEffects() || MI->isInlineAsm()) continue; unsigned NumD = MI->getDesc().getNumDefs(); if (NumD != 1) @@ -1325,8 +1325,7 @@ bool RedundantInstrElimination::processBlock(MachineBasicBlock &B, if (!BT.has(RD.Reg)) continue; const BitTracker::RegisterCell &DC = BT.lookup(RD.Reg); - auto At = MI->isPHI() ? B.getFirstNonPHI() - : MachineBasicBlock::iterator(MI); + auto At = MachineBasicBlock::iterator(MI); // Find a source operand that is equal to the result. for (auto &Op : MI->uses()) { |
