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* Fix 80 column violations.Richard Osborne2011-05-311-2/+5
| | | | llvm-svn: 132341
* Add XCore intrinsic for crc8.Richard Osborne2011-05-312-0/+16
| | | | llvm-svn: 132340
* Add XCore intrinsic for crc32.Richard Osborne2011-05-311-1/+7
| | | | llvm-svn: 132336
* Fix ssat and ssat16 encodings for ARM and Thumb. The bit position valueBruno Cardoso Lopes2011-05-314-8/+26
| | | | | | | must be encoded decremented by one. Only add encoding tests for ssat16 because ssat can't be parsed yet. llvm-svn: 132324
* This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor,Bruno Cardoso Lopes2011-05-314-6/+664
| | | | | | | | | | nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
* This patch implements the thread local storage. Implemented are GeneralBruno Cardoso Lopes2011-05-317-3/+144
| | | | | | | | Dynamic, Initial Exec and Local Exec TLS models. Patch by Sasa Stankovic llvm-svn: 132322
* Use the dwarf->llvm mapping to print register names in the cfiRafael Espindola2011-05-3033-15/+137
| | | | | | | | directives. Fixes PR9826. llvm-svn: 132317
* (1 - X) * (-2) -> (x - 1) * 2, for all positive nonzero powers of 2Stuart Hastings2011-05-301-0/+17
| | | | | | rdar://problem/6501862 llvm-svn: 132316
* Split ppc dwarf regnums into ppc64 and ppc32 flavours.Rafael Espindola2011-05-302-141/+152
| | | | llvm-svn: 132315
* Introduce the DwarfRegAlias class for declaring that two registers have theRafael Espindola2011-05-301-16/+16
| | | | | | | | | | same dwarf number. This will be used for creating a dwarf number to register mapping. The only case that needs this so far is the XMM/YMM registers that unfortunately do have the same numbers. llvm-svn: 132314
* Mark the 32 bit registers as invalid in 64 bit mode. In 64 bit mode they areRafael Espindola2011-05-301-9/+9
| | | | | | subregisters of the 64 bit ones. llvm-svn: 132313
* Remove the DwarfNumbers from the subregisters. They should use DW_OP_bit_pieceRafael Espindola2011-05-301-48/+48
| | | | | | | and for now the generic dwarf emission will automatically use the superregister numbers. llvm-svn: 132312
* Reapply r132245 with a fix for the bug that broke the darwin9/i386 build.Jakob Stoklund Olesen2011-05-303-55/+72
| | | | llvm-svn: 132309
* Emit the handler's data area. For GCC-style exceptions under Win64, theCharles Davis2011-05-301-0/+21
| | | | | | | handler's data area starts with a 4-byte reference to the personality function, followed by the DWARF LSDA. llvm-svn: 132302
* Revert r132245, "Create two BlockInfo entries when a live range is ↵Jakob Stoklund Olesen2011-05-293-71/+55
| | | | | | | | discontinuous through a block." This commit seems to have broken a darwin 9 tester. llvm-svn: 132299
* Fix PR10046 by updating LiveVariables kill info when splitting live ranges.Jakob Stoklund Olesen2011-05-291-2/+39
| | | | | | | | | | | | | This only affects targets like Mips where branch instructions may kill virtual registers. Most other targets branch on flag values, so virtual registers are not involved. The problem is that MachineBasicBlock::updateTerminator deletes branches and inserts new ones while LiveVariables keeps a list of pointers to instructions that kill virtual registers. That list wasn't properly updated in MBB::SplitCriticalEdge. llvm-svn: 132298
* On Darwin ARM, set the UNWIND_RESUME libcall to _Unwind_SjLj_Resume.John McCall2011-05-291-0/+1
| | | | | | | | | This is important for the correct lowering of unwind instructions (which doesn't matter at all) and llvm.eh.resume calls (which does). Take 2, now with more basic competence. llvm-svn: 132295
* ...this is not a good commit day for me.John McCall2011-05-291-7/+0
| | | | llvm-svn: 132294
* I didn't mean to commit these residues of a personal project.John McCall2011-05-291-1/+0
| | | | llvm-svn: 132293
* On Darwin ARM, set the UNWIND_RESUME libcall to _Unwind_SjLj_Resume.John McCall2011-05-292-0/+8
| | | | | | | This is important for the correct lowering of unwind instructions (which doesn't matter at all) and llvm.eh.resume calls (which does). llvm-svn: 132291
* Don't crash owhen ComputeLoadResult can't compute the result of the load.Nick Lewycky2011-05-291-1/+1
| | | | llvm-svn: 132290
* Obey the isVolatile bit on memory intrinsics when analyzing uses of a globalNick Lewycky2011-05-291-5/+19
| | | | | | | | | variable. Noticed by inspection. Simulate memset in EvaluateFunction where the target of the memset and the value we're setting are both the null value. Fixes PR10047! llvm-svn: 132288
* Fix warnings due to 132263; Thanks rdivacky.Nadav Rotem2011-05-291-2/+4
| | | | llvm-svn: 132285
* When generating against the Win64 EH scheme, set the handler to the GCC-specificCharles Davis2011-05-291-0/+7
| | | | | | | | | | | | | | | | handler. At this moment, only GCC-style exceptions are supported. Other kinds of exceptions, including "traditional" SEH and Microsoft Visual C++ exceptions, need more work--and an compiler exception model that isn't specific to GCC-style exceptions! In particular, I imagine that it would be possible to mix "traditional" SEH with GCC-style EH or Microsoft C++ EH. Currently LLVM has no way (beyond some target-specific defaults and whole-module compiler switches) of knowing which scheme to use when. llvm-svn: 132283
* Fix to match the dwarf register numbers that gdb uses.Rafael Espindola2011-05-291-16/+16
| | | | llvm-svn: 132278
* Dwarf register 0 is r0, remove incorrect entries.Rafael Espindola2011-05-291-2/+2
| | | | llvm-svn: 132276
* Fix this to work correctly with phis; test case to follow if this successfullyJohn McCall2011-05-291-0/+1
| | | | | | fixes self-host. llvm-svn: 132275
* Remove the dwarf numbers from the D registers. They don't have dwarf numbersRafael Espindola2011-05-291-16/+16
| | | | | | | | and should probably be encoded as DW_OP_reg 32 DW_OP_piece 4 DW_OP_reg 33 llvm-svn: 132274
* Fix ARM fast isel to correctly flag memory operands to stores. This fixesCameron Zwarich2011-05-281-5/+7
| | | | | | -verify-machineinstrs failures on several tests. llvm-svn: 132268
* Refactor the type legalizer. Switch TargetLowering to a new enum - ↵Nadav Rotem2011-05-282-33/+26
| | | | | | | | | | | LegalizeTypeAction. This patch does not change the behavior of the type legalizer. The codegen produces the same code. This infrastructural change is needed in order to enable complex decisions for vector types (needed by the vector-select patch). llvm-svn: 132263
* Erase instructions _after_ checking their type.Benjamin Kramer2011-05-281-3/+4
| | | | llvm-svn: 132256
* ConstantFoldInstOperands doesn't like compares, hand it off to instsimplify ↵Benjamin Kramer2011-05-281-0/+10
| | | | | | | | instead. Fixes PR10040. llvm-svn: 132254
* Implement and document the llvm.eh.resume intrinsic, which isJohn McCall2011-05-282-87/+223
| | | | | | | | | | | | | | | | | transformed by the inliner into a branch to the enclosing landing pad (when inlined through an invoke). If not so optimized, it is lowered DWARF EH preparation into a call to _Unwind_Resume (or _Unwind_SjLj_Resume as appropriate). Its chief advantage is that it takes both the exception value and the selector value as arguments, meaning that there is zero effort in recovering these; however, the frontend is required to pass these down, which is not actually particularly difficult. Also document the behavior of landing pads a bit better, and make it clearer that it's okay that personality functions don't always land at landing pads. This is just a fact of life. Don't write optimizations that rely on pushing things over an unwind edge. llvm-svn: 132253
* When generating code for Win64 EH, emit StartProc and EndProc directives.Charles Davis2011-05-282-0/+31
| | | | llvm-svn: 132250
* Add support for ARM ldrexd/strexd intrinsics. They both use i32 register pairsBruno Cardoso Lopes2011-05-284-5/+139
| | | | | | | | to load/store i64 values. Since there's no current support to explicitly declare such restrictions, implement it by using specific hardcoded register pairs during isel. llvm-svn: 132248
* This actually starts at offset 0, not 1.Eric Christopher2011-05-281-1/+1
| | | | llvm-svn: 132246
* Create two BlockInfo entries when a live range is discontinuous through a block.Jakob Stoklund Olesen2011-05-283-55/+71
| | | | | | | | | | | | | | | | | | | Delete the Kill and Def markers in BlockInfo. They are no longer necessary when BlockInfo describes a continuous live range. This only affects the relatively rare kind of basic block where a live range looks like this: |---x o---| Now live range splitting can pretend that it is looking at two blocks: |---x o---| This allows the code to be simplified a bit. llvm-svn: 132245
* Add SplitAnalysis::getNumLiveBlocks().Jakob Stoklund Olesen2011-05-283-5/+12
| | | | | | | | | | | It is important that this function returns the same number of live blocks as countLiveBlocks(CurLI) because live range splitting uses the number of live blocks to ensure it is making progress. This is in preparation of supporting duplicate UseBlock entries for basic blocks that have a virtual register live-in and live-out, but not live-though. llvm-svn: 132244
* Change the set of callee-saved registers for non-MIPS32 architectures specifiedAkira Hatanaka2011-05-281-9/+1
| | | | | | | | | in MipsRegisterInfo::getCalleeSavedRegs so that both registers paired for a double precision register get saved. llvm-svn: 132243
* Implement the 'M' output modifier for arm inline asm. This is fairlyEric Christopher2011-05-281-2/+27
| | | | | | | | | register allocation dependent and will occasionally break. WIP in the register allocator to model paired/etc registers. rdar://9119939 llvm-svn: 132242
* Define a wrapper node for target constant nodes (tglobaladdr, etc.).Akira Hatanaka2011-05-284-15/+27
| | | | | | Need this to prevent emitting illegal conditional move instructions. llvm-svn: 132240
* Select DW_AT_const_value size based on global variable size.Devang Patel2011-05-281-5/+13
| | | | llvm-svn: 132239
* Add 132187 back now that the real problem is fixed.Rafael Espindola2011-05-281-45/+45
| | | | llvm-svn: 132238
* Fix the root cause of the bootstrap failure:Rafael Espindola2011-05-281-1/+1
| | | | | | | | There was no way to check if a given register/mode pair was valid. We now return an error code (-2) instead of asserting. If anyone thinks that an assert at this point is really needed, we can autogen a hasValidDwarfRegNum instead. llvm-svn: 132236
* Fix the remaining atomic intrinsics to use the right register classes on Thumb2,Cameron Zwarich2011-05-271-10/+23
| | | | | | and add some basic tests for them. llvm-svn: 132235
* Stub out support for Win64-style exceptions. Note that this is merely usingCharles Davis2011-05-275-0/+99
| | | | | | | the Win64 EH mechanism to implement GCC-style exceptions. LLVM supports hardly anything else at this point! llvm-svn: 132234
* ARM asm parser wasn't able to parse a "mov" instruction while in ThumbBruno Cardoso Lopes2011-05-271-3/+5
| | | | | | | mode (only the "mov.w" variant). Now, when parsing "mov" in thumb mode, default to the Thumb 1 versions/encodings. llvm-svn: 132233
* It looks like 132187 might have broken the llvm-gcc bootstrap. Revert while ↵Rafael Espindola2011-05-271-45/+45
| | | | | | I check. llvm-svn: 132230
* Add a GR32_NOREX_NOSP register class and fix a bug where ↵Cameron Zwarich2011-05-272-2/+17
| | | | | | | | | getMatchingSuperRegClass() was saying that the matching superregister class of GR32_NOREX in GR64_NOREX_NOSP is GR64_NOREX, which drops the NOSP constraint. This fixes PR10032. llvm-svn: 132225
* Fix a regression I recently introduced by removing DwarfRegNum ofRafael Espindola2011-05-271-1/+18
| | | | | | | | | | subregisters: When a value is in a subregister, at least report the location as being the superregister. We should extend the .td files to encode the bit range so that we can produce a DW_OP_bit_piece. llvm-svn: 132224
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