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* Cleanup comments and argument types related to my previous ↵Andrew Trick2012-01-071-4/+5
| | | | | | replaceCongruentPhis checkin. llvm-svn: 147709
* Extended replaceCongruentPhis to handle mixed phi types.Andrew Trick2012-01-072-15/+63
| | | | llvm-svn: 147707
* Make the 'x' constraint work for AVX registers as well.Eric Christopher2012-01-071-3/+13
| | | | | | Fixes rdar://10614894 llvm-svn: 147704
* Missing raw_ostream.h breaks MSVC build.Andrew Trick2012-01-071-0/+1
| | | | llvm-svn: 147703
* Expose isNonConstantNegative to users of ScalarEvolution.Andrew Trick2012-01-072-20/+20
| | | | llvm-svn: 147700
* Add comment.Chad Rosier2012-01-061-0/+4
| | | | llvm-svn: 147696
* Add a comment and ensure that anyone else looking at this code doesn't startEric Christopher2012-01-061-6/+5
| | | | | | to bleed from the eyes. llvm-svn: 147695
* Use const vector references instead of a vector copy. Spotted by Devang.Eric Christopher2012-01-061-4/+4
| | | | llvm-svn: 147694
* Use -> instead of (*iter).Eric Christopher2012-01-061-10/+10
| | | | llvm-svn: 147693
* Enable aligned NEON spilling by default.Jakob Stoklund Olesen2012-01-061-1/+1
| | | | | | Experiments show this to be a small speedup for modern ARM cores. llvm-svn: 147689
* Put all IVUsers in the processed set. Allow querying IVUsers with ↵Andrew Trick2012-01-061-3/+6
| | | | | | isIVUserOrOperand. llvm-svn: 147686
* Abort AdjustBBOffsetsAfter early when possible.Jakob Stoklund Olesen2012-01-061-2/+10
| | | | llvm-svn: 147685
* SCEVExpander: hoistStep should check strict dominance.Andrew Trick2012-01-061-1/+1
| | | | llvm-svn: 147683
* Tracing to help investigate issues with SjLj spill code.Andrew Trick2012-01-061-0/+2
| | | | llvm-svn: 147682
* Initializing to false makes better sense. Thanks, David.Chad Rosier2012-01-061-1/+1
| | | | llvm-svn: 147679
* Fix uninitialized variable warning.Chad Rosier2012-01-061-1/+1
| | | | llvm-svn: 147676
* Fix uninitialized variable warning.Chad Rosier2012-01-061-1/+1
| | | | llvm-svn: 147675
* Fix a leak I noticed while reviewing the accelerator table changes. PassesEric Christopher2012-01-061-0/+5
| | | | | | | | lldb testsuite. rdar://10652330 llvm-svn: 147673
* [asan] cleanup: remove the SIGILL-related code (compiler part)Kostya Serebryany2012-01-061-68/+8
| | | | llvm-svn: 147667
* Fix typo in stringEli Bendersky2012-01-061-1/+1
| | | | llvm-svn: 147654
* As part of the ongoing work in finalizing the accelerator tables, extendEric Christopher2012-01-065-38/+110
| | | | | | | | | the debug type accelerator tables to contain the tag and a flag stating whether or not a compound type is a complete type. rdar://10652330 llvm-svn: 147651
* Fix SpeculativelyExecuteBB to either speculate all or none of the phisDan Gohman2012-01-051-140/+148
| | | | | | | | | | | | present in the bottom of the CFG triangle, as the transformation isn't ever valuable if the branch can't be eliminated. Also, unify some heuristics between SimplifyCFG's multiple if-converters, for consistency. This fixes rdar://10627242. llvm-svn: 147630
* PR11705, part 2: globalopt shouldn't put inttoptr/ptrtoint operations into ↵Eli Friedman2012-01-051-10/+20
| | | | | | global initializers if there's an implied extension or truncation. llvm-svn: 147625
* Link symbols with different visibilities according to the rules in theRafael Espindola2012-01-051-24/+54
| | | | | | | | System V Application Binary Interface. This lets us use -fvisibility-inlines-hidden with LTO. Fixes PR11697. llvm-svn: 147624
* Revert r56315. When the instruction to speculate is a load, thisDan Gohman2012-01-051-26/+2
| | | | | | | | code can incorrectly move the load across a store. This never happens in practice today, but only because the current heuristics accidentally preclude it. llvm-svn: 147623
* Kill ObjectCodeEmitter and BinaryObject, they were unused and superseded by MC.Benjamin Kramer2012-01-052-142/+0
| | | | llvm-svn: 147618
* SCCCaptured is trivially false on entry to this loop and not modified inside it.Nick Lewycky2012-01-051-1/+1
| | | | | | Eliminate the dead test for it on each loop iteration. No functionality change. llvm-svn: 147616
* Remove the old ELF writer.Rafael Espindola2012-01-0510-2223/+3
| | | | llvm-svn: 147615
* A small re-factored JIT/MCJIT::getPointerToNamedFunction(), so it could be ↵Danil Malyshev2012-01-053-4/+10
| | | | | | called with the base class. llvm-svn: 147610
* revert r147542 after comments from Joerg SonnenbergerSebastian Pop2012-01-054-18/+7
| | | | llvm-svn: 147608
* Remove an unused variable.Chandler Carruth2012-01-051-1/+0
| | | | llvm-svn: 147605
* Prevent a DAGCombine from firing where there are two uses ofChandler Carruth2012-01-051-1/+3
| | | | | | | | | a combined-away node and the result of the combine isn't substantially smaller than the input, it's just canonicalized. This is the first part of a significant (7%) performance gain for Snappy's hot decompression loop. llvm-svn: 147604
* Mark scalar FMA4 instructions as ignoring the VEX.L bit.Craig Topper2012-01-051-4/+4
| | | | llvm-svn: 147602
* Peephole optimization of ptest-conditioned branch in X86 arch. Performs ↵Victor Umansky2012-01-052-0/+142
| | | | | | | | | instruction combining of sequences generated by ptestz/ptestc intrinsics to ptest+jcc pair for SSE and AVX. Testing: passed 'make check' including LIT tests for all sequences being handled (both SSE and AVX) Reviewers: Evan Cheng, David Blaikie, Bruno Lopes, Elena Demikhovsky, Chad Rosier, Anton Korobeynikov llvm-svn: 147601
* Minor postra scheduler cleanup. It could result in more precise ↵Andrew Trick2012-01-051-25/+19
| | | | | | antidependence latency on ARM in exceedingly rare cases. llvm-svn: 147594
* Replace the uint64_t -> double convertion algorithm with one that's more ↵Bill Wendling2012-01-051-52/+38
| | | | | | | | | | | | | | | | | | | | | | efficient. This small bit of ASM code is sufficient to do what the old algorithm did: movq %rax, %xmm0 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U } subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 } #ifdef __SSE3__ haddpd %xmm0, %xmm0 #else pshufd $0x4e, %xmm0, %xmm1 addpd %xmm1, %xmm0 #endif It's arguably faster. One caveat, the 'haddpd' instruction isn't very fast on all processors. <rdar://problem/7719814> llvm-svn: 147593
* Reapply r146997, "Heed spill slot alignment on ARM."Jakob Stoklund Olesen2012-01-052-3/+4
| | | | | | | | | | | | Now that canRealignStack() understands frozen reserved registers, it is safe to use it for aligned spill instructions. It will only return true if the registers reserved at the beginning of register allocation allow for dynamic stack realignment. <rdar://problem/10625436> llvm-svn: 147579
* Avoid reserving an ARM base pointer during register allocation.Jakob Stoklund Olesen2012-01-051-2/+17
| | | | | | | | | | | | | | | | | Once register allocation has started the reserved registers are frozen. Fix the ARM canRealignStack() hook to respect the frozen register state. Now the hook returns false if register allocation was started with frame pointer elimination enabled. It also returns false if register allocation started without a reserved base pointer, and stack realignment would require a base pointer. This bug was breaking oggenc on armv6. No test case, an upcoming patch will use this functionality to realign the stack for spill slots when possible. llvm-svn: 147578
* Freeze reserved registers before starting register allocation.Jakob Stoklund Olesen2012-01-054-0/+7
| | | | | | | | | | | The register allocators don't currently support adding reserved registers while they are running. Extend the MRI API to keep track of the set of reserved registers when register allocation started. Target hooks like hasFP() and needsStackRealignment() can look at this set to avoid reserving more registers during register allocation. llvm-svn: 147577
* Generalize isSafeToSpeculativelyExecute to work on arbitraryDan Gohman2012-01-041-1/+5
| | | | | | | Values, rather than just Instructions, since it's interesting for ConstantExprs too. llvm-svn: 147560
* Silence warnings of a mysterious compiler that still defaults to C89.Benjamin Kramer2012-01-041-2/+2
| | | | llvm-svn: 147553
* use getHostTriple instead of getDefaultTargetTriple in getClosestTargetForJITSebastian Pop2012-01-044-7/+18
| | | | | | | | | | Get back getHostTriple. For JIT compilation, use the host triple instead of the default target: this fixes some JIT testcases that used to fail when the compiler has been configured as a cross compiler. llvm-svn: 147542
* Enable -soft-float for MIPS.Akira Hatanaka2012-01-041-7/+10
| | | | llvm-svn: 147541
* Remove pointless asserts.Nick Lewycky2012-01-041-2/+0
| | | | llvm-svn: 147529
* Teach instcombine all sorts of great stuff about shifts that have exact, nuw orNick Lewycky2012-01-042-8/+59
| | | | | | nsw bits on them. llvm-svn: 147528
* Allow vector shuffle normalizing to use concat vector even if the sources ↵Craig Topper2012-01-041-11/+24
| | | | | | are commuted in the shuffle mask. llvm-svn: 147527
* Implement VECTOR_SHUFFLE canonicalizations during DAG combine.Craig Topper2012-01-041-2/+50
| | | | llvm-svn: 147525
* Rename immLUiOpnd.Akira Hatanaka2012-01-042-3/+3
| | | | llvm-svn: 147519
* - Define base classes for Jump-and-link instructions and make 32-bit and 64-bitAkira Hatanaka2012-01-042-42/+27
| | | | | | | | | versions derive from them. - JALR64 is not needed since N64 does not emit jal. - Add template parameter to BranchLink that sets the rt field. - Fix the set of temporary registers for O32 and N64. llvm-svn: 147518
* Have getRegForInlineAsmConstraint return the correct register class when targetAkira Hatanaka2012-01-041-4/+9
| | | | | | is Mips64. llvm-svn: 147516
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