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* Use fp unpack instructions to unpack int types. Until we have AVX2, thisBruno Cardoso Lopes2011-08-092-8/+34
| | | | | | is the best we can do for these patterns. This fix PR10554. llvm-svn: 137161
* Fix a couple ridiculous copy-paste errors. rdar://9914773 .Eli Friedman2011-08-091-2/+2
| | | | llvm-svn: 137160
* Add a C interface to PassManagerBuilder. It is missing the addExtensionRafael Espindola2011-08-091-0/+80
| | | | | | | functionality since in the C api a pass is created and added to a pass manager in a single call. llvm-svn: 137159
* Don't truncate MachO addresses.Jim Grosbach2011-08-091-1/+1
| | | | | | | | | | | | | | Assigned symbol addresses get truncated to 32-bits, even on 64-bit platforms. That's obviously bogus. For example, .globl _foo .equ _foo, 0x987654321ULL rdar://9922863 llvm-svn: 137158
* ARM Disassembler: sign extend branch immediates.Benjamin Kramer2011-08-091-2/+2
| | | | | | Not sure about BLXi, but this is what the old disassembler did. llvm-svn: 137156
* Silence an false-positive warning.Owen Anderson2011-08-091-1/+1
| | | | llvm-svn: 137154
* Don't generate the old-style disassembler in CMake builds either.Owen Anderson2011-08-091-1/+0
| | | | llvm-svn: 137153
* The new ARM disassembler disassembles "bx lr" as a special BX_ret ↵Benjamin Kramer2011-08-091-10/+0
| | | | | | instruction so target specific analysis isn't needed anymore. llvm-svn: 137151
* Don't continue generating the old-style decoder file.Owen Anderson2011-08-091-3/+2
| | | | llvm-svn: 137150
* ARM fix typo in pre-indexed store lowering.Jim Grosbach2011-08-091-1/+1
| | | | | | rdar://9915869 llvm-svn: 137148
* Attempt to fix CMake build.Owen Anderson2011-08-091-0/+1
| | | | llvm-svn: 137147
* Tighten Thumb1 branch predicate decoding.Owen Anderson2011-08-091-0/+3
| | | | llvm-svn: 137146
* Replace the existing ARM disassembler with a new one based on the ↵Owen Anderson2011-08-0912-7229/+2417
| | | | | | | | | | FixedLenDecoderEmitter. This new disassembler can correctly decode all the testcases that the old one did, though some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in operand checking as the old one was. llvm-svn: 137144
* Put Darwin-specific code inside an __APPLE__ ifdef.Bob Wilson2011-08-091-0/+2
| | | | llvm-svn: 137137
* Revert r137134. It breaks some code as Eli pointed out.Bill Wendling2011-08-091-1/+1
| | | | llvm-svn: 137135
* Print out the variable declaration only if it is a declaration. Otherwise, aBill Wendling2011-08-091-1/+1
| | | | | | | 'static' variable will be emitted twice. PR10081 llvm-svn: 137134
* Inflate register classes after coalescing.Jakob Stoklund Olesen2011-08-091-2/+35
| | | | | | | | | | | | | | | | | | | | | | | Coalescing can remove copy-like instructions with sub-register operands that constrained the register class. Examples are: x86: GR32_ABCD:sub_8bit_hi -> GR32 arm: DPR_VFP2:ssub0 -> DPR Recompute the register class of any virtual registers that are used by less instructions after coalescing. This affects code generation for the Cortex-A8 where we use NEON instructions for f32 operations, c.f. fp_convert.ll: vadd.f32 d16, d1, d0 vcvt.s32.f32 d0, d16 The register allocator is now free to use d16 for the temporary, and that comes first in the allocation order because it doesn't interfere with any s-registers. llvm-svn: 137133
* Reapply a more appropriate solution than in r137114. AVX supportsBruno Cardoso Lopes2011-08-091-0/+10
| | | | | | | v4f64 = sitofp v4i32. This fix PR10559. Also add support for v4i32 = fptosi v4f64. llvm-svn: 137128
* Revert r137114Bruno Cardoso Lopes2011-08-091-21/+1
| | | | llvm-svn: 137127
* PTX: Add initial support for device function callsJustin Holewinski2011-08-096-3/+144
| | | | | | - Calls are supported on SM 2.0+ for function with no return values llvm-svn: 137125
* Move CalculateRegClass to MRI::recomputeRegClass.Jakob Stoklund Olesen2011-08-093-34/+36
| | | | | | | | This function doesn't have anything to do with spill weights, and MRI already has functions for manipulating the register class of a virtual register. llvm-svn: 137123
* Emitting ARM build attributes and values as ULEB, rather than char.Renato Golin2011-08-091-11/+67
| | | | llvm-svn: 137115
* Handle sitofp between v4f64 <- v4i32. Fix PR10559Bruno Cardoso Lopes2011-08-091-1/+21
| | | | llvm-svn: 137114
* Recognize the UNAME_RELEASE environment variable to match Darwin's uname.Bob Wilson2011-08-091-0/+6
| | | | | | | | When this variable is set, "uname -r" will return its value instead of the real OS version. Make this affect LLVM's triple for consistency. <rdar://problem/9919167> llvm-svn: 137111
* LoopUnroll looks like it has some stale code. Remove it to prove my sanity ↵Andrew Trick2011-08-091-6/+1
| | | | | | and avoid further confusion. llvm-svn: 137106
* Add support for avx vector fextendBruno Cardoso Lopes2011-08-091-1/+6
| | | | llvm-svn: 137105
* Add AVX versions of 128-bit sitofp and fptosiBruno Cardoso Lopes2011-08-091-0/+4
| | | | llvm-svn: 137104
* Add two patterns to match special vmovss and vmovsd cases. Also fixBruno Cardoso Lopes2011-08-091-10/+45
| | | | | | | the patterns already there to be more strict regarding the predicate. This fixes PR10558 llvm-svn: 137100
* There is only one instance of this placeholder being created. Just use thatBill Wendling2011-08-091-6/+6
| | | | | | instead of a vector. llvm-svn: 137099
* Remove an instance where the 'unwind' instruction was created.Bill Wendling2011-08-091-2/+10
| | | | | | | | | The 'unwind' instruction was acting essentially as a placeholder, because it would be replaced at the end of this function by a branch to the "unwind handler". The 'unwind' instruction is going away, so use 'unreachable' instead, which serves the same purpose as a placeholder. llvm-svn: 137098
* Print variable's inline location in debug output.Devang Patel2011-08-091-2/+5
| | | | llvm-svn: 137096
* Provide method to print variable's extended name which includes inline location.Devang Patel2011-08-091-1/+37
| | | | llvm-svn: 137095
* Rename member variables to follow coding standards.Jakob Stoklund Olesen2011-08-092-231/+232
| | | | | | No functional change. llvm-svn: 137094
* Add missing attributes to the C++ backend's output.Bill Wendling2011-08-091-0/+3
| | | | llvm-svn: 137091
* Make LowerVSETCC aware of AVX types and add patterns to match them.Bruno Cardoso Lopes2011-08-092-3/+35
| | | | llvm-svn: 137090
* Move the RegisterCoalescer private to its implementation file.Jakob Stoklund Olesen2011-08-092-142/+123
| | | | | | RegisterCoalescer.h still has the CoalescerPair class interface. llvm-svn: 137088
* Refer to the RegisterCoalescer pass by ID.Jakob Stoklund Olesen2011-08-096-13/+8
| | | | | | | A public interface is no longer needed since RegisterCoalescer is not an analysis any more. llvm-svn: 137082
* ARM parsing and encoding for LDRBT instruction.Jim Grosbach2011-08-081-11/+28
| | | | | | | Fix the instruction representation to correctly only allow post-indexed form. Add tests. llvm-svn: 137074
* Thumb1 BL instructions encoding 22 bits of displacement, not 21.Owen Anderson2011-08-081-1/+4
| | | | llvm-svn: 137073
* Indicate that there are changes if runOfFunction returns saying that there are.Bill Wendling2011-08-081-1/+1
| | | | | | Patch by Jingyue! llvm-svn: 137072
* Implement isLoadFromStackSlotPostFE and isStoreToStackSlotPostFE for ARM.Jakob Stoklund Olesen2011-08-082-0/+16
| | | | | | They improve the verbose assembly. llvm-svn: 137069
* Add support for several vector shifts operations while in AVX mode. Fix PR10581Bruno Cardoso Lopes2011-08-081-10/+52
| | | | llvm-svn: 137067
* ARM load/store label parsing.Jim Grosbach2011-08-081-0/+14
| | | | | | | Allow labels for load/store instructions when parsing. There's encoding issues, still, so this doesn't work all the way through, yet. llvm-svn: 137064
* Hoist hasLoadFromStackSlot and hasStoreToStackSlot.Jakob Stoklund Olesen2011-08-083-57/+36
| | | | | | | These the methods are target-independent since they simply scan the memory operands. They can live in TargetInstrInfoImpl. llvm-svn: 137063
* Fix encodings for Thumb ASR and LSR immediate operands. They encode the ↵Owen Anderson2011-08-084-12/+35
| | | | | | range 1-32, with 32 encoded as 0. llvm-svn: 137062
* Fix up the patterns for SXTB, SXTH, UXTB, and UXTH so that they are ↵Eli Friedman2011-08-081-5/+6
| | | | | | correctly active without HasT2ExtractPack. PR10611. llvm-svn: 137061
* Pacify virtual dtor warnings and cmake buildbots.Benjamin Kramer2011-08-081-0/+1
| | | | llvm-svn: 137060
* Add MCInstrAnalysis class. This allows the targets to specify own versions ↵Benjamin Kramer2011-08-082-0/+73
| | | | | | | | | of MCInstrDescs functions. - Add overrides for ARM. - Teach llvm-objdump to use this instead of plain MCInstrDesc. llvm-svn: 137059
* Simplify by creating parent first.Devang Patel2011-08-081-19/+14
| | | | llvm-svn: 137056
* Don't clobber pending ST regs when FP regs are killed.Jakob Stoklund Olesen2011-08-081-0/+20
| | | | | | | | | | | | | | | | | | | X86FloatingPoint keeps track of pending ST registers for an upcoming inline asm instruction with fixed stack register constraints. It does this by remembering which FP register holds the value that should appear at a fixed stack position for the inline asm. When that FP register is killed before the inline asm, make sure to duplicate it to a scratch register, so the ST register still has a live FP reference. This could happen when the same FP register was copied to two ST registers, or when a spill instruction is inserted between the ST copy and the inline asm. This fixes PR10602. llvm-svn: 137050
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