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* [Hexagon] Adding classes and load unsigned byte instruction, updating usages.Colin LeMahieu2014-12-226-28/+123
| | | | llvm-svn: 224730
* [x86] Add vector @llvm.ctpop intrinsic custom loweringBruno Cardoso Lopes2014-12-221-0/+152
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, when ctpop is supported for scalar types, the expansion of @llvm.ctpop.vXiY uses vector element extractions, insertions and individual calls to @llvm.ctpop.iY. When not, expansion with bit-math operations is used for the scalar calls. Local haswell measurements show that we can improve vector @llvm.ctpop.vXiY expansion in some cases by using a using a vector parallel bit twiddling approach, based on: v = v - ((v >> 1) & 0x55555555); v = (v & 0x33333333) + ((v >> 2) & 0x33333333); v = ((v + (v >> 4) & 0xF0F0F0F) v = v + (v >> 8) v = v + (v >> 16) v = v & 0x0000003F (from http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel) When scalar ctpop isn't supported, the approach above performs better for v2i64, v4i32, v4i64 and v8i32 (see numbers below). And even when scalar ctpop is supported, this approach performs ~2x better for v8i32. Here, x86_64 implies -march=corei7-avx without ctpop and x86_64h includes ctpop support with -march=core-avx2. == [x86_64h - new] v8i32: 0.661685 v4i32: 0.514678 v4i64: 0.652009 v2i64: 0.324289 == [x86_64h - old] v8i32: 1.29578 v4i32: 0.528807 v4i64: 0.65981 v2i64: 0.330707 == [x86_64 - new] v8i32: 1.003 v4i32: 0.656273 v4i64: 1.11711 v2i64: 0.754064 == [x86_64 - old] v8i32: 2.34886 v4i32: 1.72053 v4i64: 1.41086 v2i64: 1.0244 More work for other vector types will come next. llvm-svn: 224725
* Remove unused header. NFC.Juergen Ributzka2014-12-221-1/+0
| | | | llvm-svn: 224722
* [C API] Expose LLVMGetGlobalValueAddress and LLVMGetFunctionAddress.Peter Zotov2014-12-221-0/+8
| | | | | | Patch by Ramkumar Ramachandra <artagnon@gmail.com> llvm-svn: 224720
* [CodeGenPrepare] Handle properly the promotion of operands when this does notQuentin Colombet2014-12-221-3/+7
| | | | | | | | | generate instructions. Fixes PR21978. Related to <rdar://problem/18310086> llvm-svn: 224717
* AVX-512: Added all forms of BLENDM instructions,Elena Demikhovsky2014-12-223-55/+120
| | | | | | intrinsics, encoding tests for AVX-512F and skx instructions. llvm-svn: 224707
* Lower multiply-negate operation to mneg on AArch64Karthik Bhat2014-12-221-0/+4
| | | | | | | | | | | This patch pattern matches code such as- neg w8, w8 mul w8, w9, w8 to mneg w8, w8, w9 Review: http://reviews.llvm.org/D6754 llvm-svn: 224706
* The leak detector is dead, long live asan and valgrind.Rafael Espindola2014-12-2210-146/+0
| | | | | | | In resent times asan and valgrind have found way more memory management bugs in llvm than the special purpose leak detector. llvm-svn: 224703
* CodeGen: minor style tweaks to SSPSaleem Abdulrasool2014-12-211-13/+15
| | | | | | Clean up some style related things in the StackProtector CodeGen. NFC. llvm-svn: 224693
* [X86] Add hasSideEffects = 0 to CALLpcrel16. This matches what is inferred ↵Craig Topper2014-12-211-4/+5
| | | | | | from patterns for the 32-bit version. llvm-svn: 224692
* Enable (sext x) == C --> x == (trunc C) combineMatt Arsenault2014-12-212-30/+28
| | | | | | | | | Extend the existing code which handles this for zext. This makes this more useful for targets with ZeroOrNegativeOne BooleanContent and obsoletes a custom combine SI uses for i1 setcc (sext(i1), 0, setne) since the constant will now be shrunk to i1. llvm-svn: 224691
* [X86] Swap operand order in Intel syntax on a bunch of aliases.Craig Topper2014-12-201-18/+18
| | | | llvm-svn: 224687
* [X86] Swap operand order of imul aliases in Intel syntax. Also disable ↵Craig Topper2014-12-201-6/+6
| | | | | | printing of the alias instead of the real instruction. llvm-svn: 224686
* [X86] Remove '*' from asm strings in far call/jump aliases for Intel syntax.Craig Topper2014-12-201-11/+11
| | | | llvm-svn: 224685
* [X86] Don't swap the order of segment and offset in immediate form of far ↵Craig Topper2014-12-201-4/+4
| | | | | | call/jump in Intel syntax. llvm-svn: 224684
* CodeGen: constify and use range loop for SSPSaleem Abdulrasool2014-12-201-8/+4
| | | | | | Use range-based for loop and constify the iterators. NFC. llvm-svn: 224683
* ARM: further improve deprecated diagnosis (LDM)Saleem Abdulrasool2014-12-202-1/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ARM ARM states: LDM/LDMIA/LDMFD: The SP can be in the list. However, ARM deprecates using these instructions with SP in the list. ARM deprecates using these instructions with both the LR and the PC in the list. LDMDA/LDMFA/LDMDB/LDMEA/LDMIB/LDMED: The SP can be in the list. However, instructions that include the SP in the list are deprecated. Instructions that include both the LR and the PC in the list are deprecated. POP: The SP can only be in the list before ARMv7. ARM deprecates any use of ARM instructions that include the SP, and the value of the SP after such an instruction is UNKNOWN. ARM deprecates the use of this instruction with both the LR and the PC in the list. Attempt to diagnose use of deprecated forms of these instructions. This mirrors the previous changes to diagnose use of the deprecated forms of STM in ARM mode. llvm-svn: 224682
* [X86] Immediate forms of far call/jump are not valid in x86-64.Craig Topper2014-12-201-16/+20
| | | | llvm-svn: 224678
* InstCombine: Squash an icmp+select into bitwise arithmeticDavid Majnemer2014-12-201-6/+24
| | | | | | | | | (X & INT_MIN) == 0 ? X ^ INT_MIN : X into X | INT_MIN (X & INT_MIN) != 0 ? X ^ INT_MIN : X into X & INT_MAX This fixes PR21993. llvm-svn: 224676
* InstSimplify: Don't bother if getScalarSizeInBits returns zeroDavid Majnemer2014-12-201-4/+5
| | | | | | | getScalarSizeInBits returns zero when the comparison operands are not integral. No functionality change intended. llvm-svn: 224675
* Simplify the codeDavid Majnemer2014-12-201-41/+25
| | | | | | No functionality change intended. llvm-svn: 224673
* InstSimplify: Optimize away pointless comparisonsDavid Majnemer2014-12-201-2/+38
| | | | | | | | | (X & INT_MIN) ? X & INT_MAX : X into X & INT_MAX (X & INT_MIN) ? X : X & INT_MAX into X (X & INT_MIN) ? X | INT_MIN : X into X (X & INT_MIN) ? X : X | INT_MIN into X | INT_MIN llvm-svn: 224669
* [SROA] Run clang-format over the entire SROA pass as I wrote it beforeChandler Carruth2014-12-201-157/+138
| | | | | | | | | | | | much of the glory of clang-format, and now any time I touch it I risk introducing formatting changes as part of a functional commit. Also, clang-format is *way* better at formatting my code than I am. Most of this is a huge improvement although I reverted a couple of places where I hit a clang-format bug with lambdas that has been filed but not (fully) fixed. llvm-svn: 224666
* LiveIntervalAnalysis: No kill flags for partially undefined uses.Matthias Braun2014-12-201-24/+68
| | | | | | | | | We must not add kill flags when reading a vreg with some undefined subregisters, if subreg liveness tracking is enabled. This is because the register allocator may reuse these undefined subregisters for other values which are not killed. llvm-svn: 224664
* LiveIntervalAnalysis: cleanup addKills(), NFCMatthias Braun2014-12-201-19/+18
| | | | | | | | - Use more const modifiers - Use references for things that can't be nullptr - Improve some variable names llvm-svn: 224663
* Remove unused variable and initialization.Eric Christopher2014-12-201-4/+1
| | | | llvm-svn: 224655
* Remove unused variable, initializer, and accessor.Eric Christopher2014-12-192-10/+4
| | | | llvm-svn: 224650
* R600: Remove outdated commentMatt Arsenault2014-12-191-4/+0
| | | | llvm-svn: 224648
* Masked load and store codegen - fixed 128-bit vectorsElena Demikhovsky2014-12-193-20/+71
| | | | | | | The codegen failed on 128-bit types on AVX2. I added patterns and in td files and tests. llvm-svn: 224647
* R600/SI: Only form min/max with 1 use.Matt Arsenault2014-12-191-1/+1
| | | | | | | If the condition is used for something else, this increases the number of instructions. llvm-svn: 224646
* EH: Sink computation of local PadMap variable into function that uses itReid Kleckner2014-12-192-17/+15
| | | | | | No functionality change. llvm-svn: 224635
* Add printing the LC_ROUTINES load commands with llvm-objdump’s ↵Kevin Enderby2014-12-191-0/+10
| | | | | | -private-headers. llvm-svn: 224627
* Add the ExceptionHandling::MSVC enumerationReid Kleckner2014-12-195-13/+15
| | | | | | | | | | | | | | | It is intended to be used for a family of personality functions that have similar IR preparation requirements. Typically when interoperating with MSVC personality functions, bits of functionality need to be outlined from the main function into helper functions. There is also usually more than one landing pad per invoke, which does not match the LLVM IR landingpad representation. None of this is implemented yet. This change just adds a new enum that is active for *-windows-msvc and delegates to the EH removal preparation pass. No functionality change for other targets. llvm-svn: 224625
* Model sqrtss as a binary operation with one source operand tied to the ↵Sanjay Patel2014-12-191-58/+12
| | | | | | | | | | | destination (PR14221) This is a continuation of r167064 ( http://llvm.org/viewvc/llvm-project?view=revision&revision=167064 ). That patch started to fix PR14221 ( http://llvm.org/bugs/show_bug.cgi?id=14221 ), but it was not completed. Differential Revision: http://reviews.llvm.org/D6330 llvm-svn: 224624
* R600/SI: isLegalOperand() shouldn't check constant bus for SALU instructionsTom Stellard2014-12-191-1/+1
| | | | | | | The constant bus restrictions only apply to VALU instructions. This enables SIFoldOperands to fold immediates into SALU instructions. llvm-svn: 224623
* R600/SI: Make sure non-inline constants aren't folded into mubuf soffset operandTom Stellard2014-12-194-17/+25
| | | | | | | | mubuf instructions now define the soffset field using the SCSrc_32 register class which indicates that only SGPRs and inline constants are allowed. llvm-svn: 224622
* Remove isSubroutineType test for isCompositeType, getTag() is enough.Yaron Keren2014-12-191-1/+1
| | | | llvm-svn: 224621
* Add printing the LC_SUB_CLIENT load command with llvm-objdump’s ↵Kevin Enderby2014-12-191-0/+5
| | | | | | -private-headers. llvm-svn: 224616
* [Hexagon] Removing old variants of instructions and updating references.Colin LeMahieu2014-12-196-161/+13
| | | | llvm-svn: 224612
* merge consecutive stores of extracted vector elementsSanjay Patel2014-12-191-4/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a path to DAGCombiner::MergeConsecutiveStores() to combine multiple scalar stores when the store operands are extracted vector elements. This is a partial fix for PR21711 ( http://llvm.org/bugs/show_bug.cgi?id=21711 ). For the new test case, codegen improves from: vmovss %xmm0, (%rdi) vextractps $1, %xmm0, 4(%rdi) vextractps $2, %xmm0, 8(%rdi) vextractps $3, %xmm0, 12(%rdi) vextractf128 $1, %ymm0, %xmm0 vmovss %xmm0, 16(%rdi) vextractps $1, %xmm0, 20(%rdi) vextractps $2, %xmm0, 24(%rdi) vextractps $3, %xmm0, 28(%rdi) vzeroupper retq To: vmovups %ymm0, (%rdi) vzeroupper retq Patch reviewed by Nadav Rotem. Differential Revision: http://reviews.llvm.org/D6698 llvm-svn: 224611
* [Hexagon] Adding bit extraction and table indexing instructions.Colin LeMahieu2014-12-191-0/+101
| | | | llvm-svn: 224610
* [Hexagon] Adding bit insertion instructions.Colin LeMahieu2014-12-191-0/+65
| | | | llvm-svn: 224609
* [Hexagon] Adding more xtype shift instructions.Colin LeMahieu2014-12-191-0/+107
| | | | llvm-svn: 224608
* Add printing the LC_SUB_LIBRARY load command with llvm-objdump’s ↵Kevin Enderby2014-12-191-0/+5
| | | | | | -private-headers. llvm-svn: 224607
* [Hexagon] Adding xtype shift instructions.Colin LeMahieu2014-12-191-0/+198
| | | | llvm-svn: 224604
* [Hexagon] Adding transfers to and from control registers.Colin LeMahieu2014-12-192-0/+65
| | | | llvm-svn: 224599
* [Hexagon] Adding doubleregs for control registers. Renaming control ↵Colin LeMahieu2014-12-194-22/+66
| | | | | | register class. llvm-svn: 224598
* [DebugInfo] Move all DWARF headers to the public include directory.Frederic Riss2014-12-1932-1608/+26
| | | | | | | | | | dsymutil needs access to DWARF specific inforamtion, the small DIContext wrapper isn't sufficient. Other DWARF consumers might want to use it too (I'm looking at you lldb). Differential Revision: http://reviews.llvm.org/D6694 llvm-svn: 224594
* [BBVectorize] Remove two more redundant assignments.Tilmann Scheller2014-12-191-2/+0
| | | | | | Found by the Clang static analyzer. llvm-svn: 224590
* [BBVectorize] Remove redundant assignment.Tilmann Scheller2014-12-191-1/+0
| | | | | | Found by the Clang static analyzer. llvm-svn: 224589
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