summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
* [X86] Remove execute permissions from a couple files.Craig Topper2017-09-212-0/+0
| | | | llvm-svn: 313863
* [X86] Remove windows line endings.Craig Topper2017-09-211-919/+919
| | | | llvm-svn: 313862
* [X86] Remove unused tablegen class.Craig Topper2017-09-211-7/+0
| | | | llvm-svn: 313861
* Revert "Re-enable "[IRCE] Identify loops with latch comparison against ↵Serguei Katkov2017-09-211-51/+13
| | | | | | | | | | current IV value"" Revert the patch causing the functional failures. The patch owner is notified with test cases which fail. Test case has been provided to Maxim offline. llvm-svn: 313857
* [llvm-cov] Improve error messaging for function mismatchesVedant Kumar2017-09-211-2/+3
| | | | | | | | | Passing "-dump" to llvm-cov will now print more detailed information about function hash and counter mismatches. This should make it easier to debug *.profdata files which contain incorrect records, and to debug other scenarios where coverage goes missing due to mismatch issues. llvm-svn: 313853
* AMDGPU: Fix crash on immediate operandMatt Arsenault2017-09-211-1/+5
| | | | | | | | We can have a v_mac with an immediate src0. We can still fold if it's an inline immediate, otherwise it already uses the constant bus. llvm-svn: 313852
* [X86] Replace a condition that can never be true with an assert.Craig Topper2017-09-211-2/+2
| | | | llvm-svn: 313848
* [SelectionDAG] Replace a flag that can never be true with an assert.Craig Topper2017-09-211-3/+2
| | | | llvm-svn: 313847
* [InstCombine] Teach getDemandedBitsLHSMask to handle constant splat vectorsCraig Topper2017-09-201-11/+7
| | | | | | | | This replaces a ConstantInt dyn_cast with m_APInt Differential Revision: https://reviews.llvm.org/D38100 llvm-svn: 313840
* [SelectionDAG] Use APInt::getActivebits instead of Bitwidth - leading zeros.Craig Topper2017-09-201-1/+1
| | | | llvm-svn: 313839
* [WebAssembly] Weak symbols should be defined in SF_GlobalSam Clegg2017-09-201-1/+1
| | | | | | | | | | | | Summary: This manifested itself in lld since it meant that weak symbols were not appearing in archive symbol tables. Subscribers: jfb, dschuff, jgravelle-google, aheejin Differential Revision: https://reviews.llvm.org/D38111 llvm-svn: 313838
* [MSan] Disable sanitization for __sanitizer_dtor_callback.Matt Morehouse2017-09-201-0/+1
| | | | | | | | | | | | | | | | Summary: Eliminate unnecessary instrumentation at __sanitizer_dtor_callback call sites. Fixes https://github.com/google/sanitizers/issues/861. Reviewers: eugenis, kcc Reviewed By: eugenis Subscribers: vitalybuka, llvm-commits, cfe-commits, hiraditya Differential Revision: https://reviews.llvm.org/D38063 llvm-svn: 313831
* [SimplifyCFG] don't create a no-op subtractSanjay Patel2017-09-201-2/+6
| | | | | | | | | | I noticed this inefficiency while investigating PR34603: https://bugs.llvm.org/show_bug.cgi?id=34603 This fix will likely push another bug (we don't maintain state of 'LateSimplifyCFG') into hiding, but I'll try to clean that up with a follow-up patch anyway. llvm-svn: 313829
* [IR] Add llvm.dbg.addr, a control-dependent version of llvm.dbg.declareReid Kleckner2017-09-207-99/+132
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This implements the design discussed on llvm-dev for better tracking of variables that live in memory through optimizations: http://lists.llvm.org/pipermail/llvm-dev/2017-September/117222.html This is tracked as PR34136 llvm.dbg.addr is intended to be produced and used in almost precisely the same way as llvm.dbg.declare is today, with the exception that it is control-dependent. That means that dbg.addr should always have a position in the instruction stream, and it will allow passes that optimize memory operations on local variables to insert llvm.dbg.value calls to reflect deleted stores. See SourceLevelDebugging.rst for more details. The main drawback to generating DBG_VALUE machine instrs is that they usually cause LLVM to emit a location list for DW_AT_location. The next step will be to teach DwarfDebug.cpp how to recognize more DBG_VALUE ranges as not needing a location list, and possibly start setting DW_AT_start_offset for variables whose lifetimes begin mid-scope. Reviewers: aprantl, dblaikie, probinson Subscribers: eraman, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D37768 llvm-svn: 313825
* [ARM] Fix some Clang-tidy modernize-use-using and Include What You Use ↵Eugene Zelenko2017-09-2017-233/+456
| | | | | | warnings; other minor fixes (NFC). llvm-svn: 313823
* Revert "Revert "ExecutionEngine: add R_AARCH64_ABS{16,32}""Saleem Abdulrasool2017-09-201-0/+12
| | | | | | | | | | | This reverts commit SVN r313668. The original test case attempted to write a pointer value into 16-bits, although the value may exceed the range representable in 16-bits. Ensure that the symbol is located in the address space such that its absolute address is representable in 16-bits. This should fix the assertion failure that was seen on the Windows hosts. llvm-svn: 313822
* [NVPTX] Implemented shfl.sync instruction and supporting intrinsics/builtins.Artem Belevich2017-09-201-1/+73
| | | | | | Differential Revision: https://reviews.llvm.org/D38090 llvm-svn: 313820
* [InstCombine] Handle (X & C2) < C1 --> (X & C2) == 0Craig Topper2017-09-201-6/+13
| | | | | | | | We already did (X & C2) > C1 --> (X & C2) != 0, if any bit set in (X & C2) will produce a result greater than C1. But there is an equivalent inverse condition with <= C1 (which will be canonicalized to < C1+1) Differential Revision: https://reviews.llvm.org/D38065 llvm-svn: 313819
* [WebAssembly] Add support for local symbol bindingsSam Clegg2017-09-202-20/+31
| | | | | | Differential Revision: https://reviews.llvm.org/D38096 llvm-svn: 313817
* [mips] Fix calculation of a branch instruction offset to escape left shift ↵Simon Atanasyan2017-09-201-3/+3
| | | | | | of negative value llvm-svn: 313815
* AMDGPU: Start selecting v_mad_mixhi_f16Matt Arsenault2017-09-204-2/+97
| | | | llvm-svn: 313814
* X86: treat SwiftCC as Win64_CC on Win64Saleem Abdulrasool2017-09-201-0/+1
| | | | | | | | | | | The Swift CC is identical to Win64 CC with the exception of swift error being passed in r12 which is a CSR. However, since this calling convention is only used in swift -> swift code, it does not impact interoperability and can be treated entirely as Win64 CC. We would previously incorrectly lower the frame setup as we did not treat the frame as conforming to Win64 specifications. llvm-svn: 313813
* AMDGPU: Add tied operands to v_mad_mix{lo|hi}_f16Matt Arsenault2017-09-202-12/+23
| | | | | | | | | These write to the low and high half of the destination register and leave the other 16-bits unchanged. This is true for most 16-bit instructions on gfx9, but we don't use that now. llvm-svn: 313812
* Remove the default subtarget from the new Nios2 port. It's unused and ↵Eric Christopher2017-09-202-9/+1
| | | | | | deprecated. llvm-svn: 313808
* AMDGPU: Start selecting v_mad_mixlo_f16Matt Arsenault2017-09-202-0/+25
| | | | | | | | Also add some tests that should be able to use v_mad_mixhi_f16, but do not yet. This is trickier because we don't really model the partial update of the register done by 16-bit instructions. llvm-svn: 313806
* AMDGPU: Fix encoding of op_sel for mad_mix* opcodesMatt Arsenault2017-09-201-3/+3
| | | | llvm-svn: 313797
* Reland "[WebAssembly] Add support for naming wasm data segments"Sam Clegg2017-09-203-3/+26
| | | | | | | | | Add adds support for naming data segments. This is useful useful linkers so that they can merge similar sections. Differential Revision: https://reviews.llvm.org/D37886 llvm-svn: 313795
* [InstCombine] Use APInt::getActiveBits() to avoid creating an APInt from a ↵Craig Topper2017-09-201-1/+1
| | | | | | trailing zero count to do a comparison. NFCI llvm-svn: 313792
* CodeGen: support SwiftError SwiftCC on Windows x64Saleem Abdulrasool2017-09-202-0/+5
| | | | | | | | | | Add support for passing SwiftError through a register on the Windows x64 calling convention. This allows the use of swifterror attributes on parameters which is used by the swift front end for the `Error` parameter. This partially enables building the swift standard library for Windows x86_64. llvm-svn: 313791
* Rename K_MIPS64 to K_GNU64Jake Ehrlich2017-09-202-9/+9
| | | | | | | This patch renames K_MIPS64 to K_GNU64 as part of a change to add support for writing archives with 64-bit indexes in the symbol table. llvm-svn: 313787
* Re-land "[DebugInfo] Insert DW_OP_deref when spilling indirect DBG_VALUEs"Reid Kleckner2017-09-201-40/+72
| | | | | | | | | | | | | After r313775, it's easier to maintain a parallel BitVector of spilled locations indexed by location number. I wasn't able to build a good reduced test case for this iteration of the bug, but I added a more direct assertion that spilled values must use frame index locations. If this bug reappears, it won't only fire on the NEON vector code that we detected it on, but on medium-sized integer-only programs as well. llvm-svn: 313786
* Revert r313771 "[SLP] Vectorize jumbled memory loads."Hans Wennborg2017-09-202-253/+83
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This broke the buildbots, e.g. http://bb.pgr.jp/builders/test-llvm-i686-linux-RA/builds/391 > Summary: > This patch tries to vectorize loads of consecutive memory accesses, accessed > in non-consecutive or jumbled way. An earlier attempt was made with patch D26905 > which was reverted back due to some basic issue with representing the 'use mask' > jumbled accesses. > > This patch fixes the mask representation by recording the 'use mask' in the usertree entry. > > Change-Id: I9fe7f5045f065d84c126fa307ef6ebe0787296df > > Subscribers: mzolotukhin > > Reviewed By: ayal > > Differential Revision: https://reviews.llvm.org/D36130 > > Review comments updated accordingly > > Change-Id: I22ab0a8a9bac9d49d74baa81a08e1e486f5e75f0 > > Added a TODO for sortLoadAccesses API > > Change-Id: I3c679bf1865422d1b45e17ea28f1992bca660b58 > > Modified the TODO for sortLoadAccesses API > > Change-Id: Ie64a66cb5f9e2a7610438abb0e750c6e090f9565 > > Review comment update for using OpdNum to insert the mask in respective location > > Change-Id: I016d0c1b29874e979efc0205bbf078991f92edce > > Fixes '-Wsign-compare warning' in LoopAccessAnalysis.cpp and code rebase > > Change-Id: I64b2ea5e68c1d7b6a028f5ef8251c5a97333f89b llvm-svn: 313781
* llvm-dwarfdump: implement --recurse-depth=<N>Adrian Prantl2017-09-205-21/+24
| | | | | | | | | | This patch implements the Darwin dwarfdump option --recurse-depth=<N>, which limits the recursion depth when selectively printing DIEs at an offset. Differential Revision: https://reviews.llvm.org/D38064 llvm-svn: 313778
* [DebugInfo] Use a MapVector to coalesce MachineOperand locationsReid Kleckner2017-09-201-56/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: The new code should be linear in the number of DBG_VALUEs, while the old code was quadratic. NFC intended. This is also hopefully a more direct expression of the problem, which is to: 1. Rewrite all virtual register operands to stack slots or physical registers 2. Uniquely number those machine operands, assigning them location numbers 3. Rewrite all uses of the old location numbers in the interval map to use the new location numbers In r313400, I attempted to track which locations were spilled in a parallel bitvector indexed by location number. My code was broken because these location numbers are not stable during rewriting. Reviewers: aprantl, hans Subscribers: hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D38068 llvm-svn: 313775
* [InstCombine] Add select simplificationsQuentin Colombet2017-09-204-52/+44
| | | | | | | | | | | | | | | | | In these cases, two selects have constant selectable operands for both the true and false components and have the same conditional expression. We then create two arithmetic operations of the same type and feed a final select operation using the result of the true arithmetic for the true operand and the result of the false arithmetic for the false operand and reuse the original conditionl expression. The arithmetic operations are naturally folded as a consequence, leaving only the newly formed select to replace the old arithmetic operation. Patch by: Michael Berg <michael_c_berg@apple.com> Differential Revision: https://reviews.llvm.org/D37019 llvm-svn: 313774
* [SLP] Vectorize jumbled memory loads.Mohammad Shahid2017-09-202-83/+253
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch tries to vectorize loads of consecutive memory accesses, accessed in non-consecutive or jumbled way. An earlier attempt was made with patch D26905 which was reverted back due to some basic issue with representing the 'use mask' jumbled accesses. This patch fixes the mask representation by recording the 'use mask' in the usertree entry. Change-Id: I9fe7f5045f065d84c126fa307ef6ebe0787296df Subscribers: mzolotukhin Reviewed By: ayal Differential Revision: https://reviews.llvm.org/D36130 Review comments updated accordingly Change-Id: I22ab0a8a9bac9d49d74baa81a08e1e486f5e75f0 Added a TODO for sortLoadAccesses API Change-Id: I3c679bf1865422d1b45e17ea28f1992bca660b58 Modified the TODO for sortLoadAccesses API Change-Id: Ie64a66cb5f9e2a7610438abb0e750c6e090f9565 Review comment update for using OpdNum to insert the mask in respective location Change-Id: I016d0c1b29874e979efc0205bbf078991f92edce Fixes '-Wsign-compare warning' in LoopAccessAnalysis.cpp and code rebase Change-Id: I64b2ea5e68c1d7b6a028f5ef8251c5a97333f89b llvm-svn: 313771
* [ThinLTO] Fix dead stripping analysis for SamplePGOTeresa Johnson2017-09-201-3/+3
| | | | | | | | | | | | | | | | | | Summary: The fix for dead stripping analysis in the case of SamplePGO indirect calls to local functions (r313151) introduced the possibility of an infinite loop. Make sure we check for the value being already live after we update it for SamplePGO indirect call handling. Reviewers: danielcdh Subscribers: mehdi_amini, inglorion, llvm-commits, eraman Differential Revision: https://reviews.llvm.org/D38086 llvm-svn: 313766
* Revert r313736: "[SLP] Vectorize jumbled memory loads."Alexander Kornienko2017-09-202-252/+83
| | | | | | | The revision breaks buildbots: http://lab.llvm.org:8011/builders/clang-x86_64-debian-fast/builds/6694/steps/test/logs/stdio llvm-svn: 313758
* Revert r313753: "Fix a -Wsign-compare warning in LoopAccessAnalysis.cpp"Alexander Kornienko2017-09-201-2/+1
| | | | llvm-svn: 313757
* Fix a -Wsign-compare warning in LoopAccessAnalysis.cppAlexander Kornienko2017-09-201-1/+2
| | | | llvm-svn: 313753
* Recommit [MachineCombiner] Update instruction depths incrementally for large ↵Florian Hahn2017-09-202-23/+90
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BBs. This version of the patch fixes an off-by-one error causing PR34596. We do not need to use std::next(BlockIter) when calling updateDepths, as BlockIter already points to the next element. Original commit message: > For large basic blocks with lots of combinable instructions, the > MachineTraceMetrics computations in MachineCombiner can dominate the compile > time, as computing the trace information is quadratic in the number of > instructions in a BB and it's relevant successors/predecessors. > In most cases, knowing the instruction depth should be enough to make > combination decisions. As we already iterate over all instructions in a basic > block, the instruction depth can be computed incrementally. This reduces the > cost of machine-combine drastically in cases where lots of instructions > are combined. The major drawback is that AFAIK, computing the critical path > length cannot be done incrementally. Therefore we only compute > instruction depths incrementally, for basic blocks with more > instructions than inc_threshold. The -machine-combiner-inc-threshold > option can be used to set the threshold and allows for easier > experimenting and checking if using incremental updates for all basic > blocks has any impact on the performance. > > Reviewers: sanjoy, Gerolf, MatzeB, efriedma, fhahn > > Reviewed By: fhahn > > Subscribers: kiranchandramohan, javed.absar, efriedma, llvm-commits > > Differential Revision: https://reviews.llvm.org/D36619 llvm-svn: 313751
* [X86][SSE] Remove unnecessary NonceMasks from combineX86ShufflesRecursively ↵Simon Pilgrim2017-09-201-25/+14
| | | | | | calls (NFCI) llvm-svn: 313743
* [SLP] Vectorize jumbled memory loads.Mohammad Shahid2017-09-202-83/+252
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch tries to vectorize loads of consecutive memory accesses, accessed in non-consecutive or jumbled way. An earlier attempt was made with patch D26905 which was reverted back due to some basic issue with representing the 'use mask' of jumbled accesses. This patch fixes the mask representation by recording the 'use mask' in the usertree entry. Change-Id: I9fe7f5045f065d84c126fa307ef6ebe0787296df Reviewers: mkuper, loladiro, Ayal, zvi, danielcdh Reviewed By: Ayal Subscribers: mzolotukhin Differential Revision: https://reviews.llvm.org/D36130 Commit after rebase for patch D36130 Change-Id: I8add1c265455669ef288d880f870a9522c8c08ab llvm-svn: 313736
* 'into' instruction should not be decoded as a valid instr in 64-bit modeAndrew V. Tischenko2017-09-201-1/+1
| | | | llvm-svn: 313735
* [X86] Remove isel checks for immediate size on floating point compare and ↵Craig Topper2017-09-203-36/+26
| | | | | | | | xop compare instructions. NFCI If these checks fail we end up not selecting an instruction at all. So we are already relying on the immediate being checked upstream of isel. So doing the check in isel is just bloat to the isel table. Interestingly, we didn't check on the AVX512 version of the instructions anyway. llvm-svn: 313724
* [AMDGPU] Fixed memory leak with inliner replacedStanislav Mekhanoshin2017-09-201-1/+3
| | | | | | Delete inliner before replacing it. llvm-svn: 313723
* AMDGPU: Move r600 only code into r600 only td fileMatt Arsenault2017-09-202-53/+54
| | | | llvm-svn: 313719
* [AMDGPU] Fix regression in test clang/test/CodeGen/backend-unsupported-error.llStanislav Mekhanoshin2017-09-201-1/+2
| | | | llvm-svn: 313718
* AMDGPU: Match load d16 hi instructionsMatt Arsenault2017-09-205-50/+161
| | | | | | | | | | | | Also starts selecting global loads for constant address in some cases. Some end up selecting to mubuf still, which requires investigation. We still get sub-optimal regalloc and extra waitcnts inserted due to not really tracking the liveness of the separate register halves. llvm-svn: 313716
* [AMDGPU] Port of HSAIL inlinerStanislav Mekhanoshin2017-09-205-1/+218
| | | | | | Differential Revision: https://reviews.llvm.org/D36849 llvm-svn: 313714
OpenPOWER on IntegriCloud