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* [indvars] Fix bugs in floating point IV range checks noticed by inspection.Andrew Trick2011-09-131-10/+10
| | | | llvm-svn: 139574
* Silence false positive uninitialized variable warnings from GCC.Benjamin Kramer2011-09-131-3/+3
| | | | llvm-svn: 139573
* Extract live range calculations from SplitKit.Jakob Stoklund Olesen2011-09-135-306/+516
| | | | | | | | SplitKit will soon need two copies of these data structures, and the algorithms will also be useful when LiveIntervalAnalysis becomes independent of LiveVariables. llvm-svn: 139572
* Add comment to clarify the behavior of a helper in DSE.Eli Friedman2011-09-131-0/+2
| | | | llvm-svn: 139571
* Correct grammar.Eli Friedman2011-09-131-1/+1
| | | | llvm-svn: 139565
* Fix the assembler strings for a couple of atomic instructions. Doesn't ↵Eli Friedman2011-09-131-2/+2
| | | | | | really matter much in practice, but it's a bit cleaner. llvm-svn: 139563
* Tidy up a bit.Jim Grosbach2011-09-121-18/+9
| | | | llvm-svn: 139559
* Fix PR10845. SUBREG_TO_REG shouldn't be used when the input andBruno Cardoso Lopes2011-09-121-8/+8
| | | | | | destination types are equal! llvm-svn: 139553
* Introduce a bit of a hack.Bill Wendling2011-09-121-15/+44
| | | | | | | | | | | | | | | | | | Splitting a landing pad takes considerable care because of PHIs and other nasties. The problem is that the jump table needs to jump to the landing pad block. However, the landing pad block can be jumped to only by an invoke instruction. So we clone the landingpad instruction into its own basic block, have the invoke jump to there. The landingpad instruction's basic block's successor is now the target for the jump table. But because of PHI nodes, we need to create another basic block for the jump table to jump to. This is definitely a hack, because the values for the PHI nodes may not be defined on the edge from the jump table. But that's okay, because the jump table is simply a construct to mimic what is happening in the CFG. So the values are mysteriously there, even though there is no value for the PHI from the jump table's edge (hence calling this a hack). llvm-svn: 139545
* Thumb2 POP's don't allow the PC as an operand, and PUSH's don't allow the SP ↵Owen Anderson2011-09-121-7/+88
| | | | | | either. llvm-svn: 139542
* Revert the wrong part of r139528, and fix testcases.Bruno Cardoso Lopes2011-09-121-4/+4
| | | | llvm-svn: 139541
* Fix encoding of PC-relative LDRSHW with an immediate offset.Owen Anderson2011-09-121-10/+19
| | | | llvm-svn: 139537
* Change a bunch of isVolatile() checks to check for atomic load/store as well.Eli Friedman2011-09-125-19/+19
| | | | | | | | No tests; these changes aren't really interesting in the sense that the logic is the same for volatile and atomic. I believe this completes all of the changes necessary for the optimizer to handle loads and stores correctly. I'm going to try and come up with some additional testing, though. llvm-svn: 139533
* There's no need to add additional predicate operands when converting a tB to ↵Owen Anderson2011-09-121-2/+0
| | | | | | a tBfar now. Fixes nightly test failures on armv6 Thumb. <rdar://problem/10110404> llvm-svn: 139531
* Fix typo.Eric Christopher2011-09-121-1/+1
| | | | llvm-svn: 139530
* Not sure how CMPPS and CMPPD had already ever worked, I guess it didn't.Bruno Cardoso Lopes2011-09-121-9/+18
| | | | | | | | | | | | However with this fix it does now. Basically the operand order for the x86 target specific node is not the same as the instruction, but since the intrinsic need that specific order at the instruction definition, just change the order during legalization. Also, there were some wrong invertions of condition codes, such as GE => LE, GT => LT, fix that too. Fix PR10907. llvm-svn: 139528
* Organize a bit the operand names for CMPPS and CMPPDBruno Cardoso Lopes2011-09-121-18/+18
| | | | llvm-svn: 139527
* Realign BLEND patterns to match the general style for patterns in .td file.Bruno Cardoso Lopes2011-09-121-45/+42
| | | | llvm-svn: 139526
* Fix 80-columnsBruno Cardoso Lopes2011-09-121-12/+16
| | | | llvm-svn: 139525
* Port more encoding tests to decoding tests, and correct an improper Thumb2 ↵Owen Anderson2011-09-122-0/+36
| | | | | | pre-indexed load decoding this uncovered. llvm-svn: 139522
* Rename -disable-iv-rewrite to -enable-iv-rewrite=false in preparation for ↵Andrew Trick2011-09-121-42/+20
| | | | | | default change. llvm-svn: 139517
* Add asserts to keep front-ends honest while encoding debug info into LLVM IR ↵Devang Patel2011-09-121-0/+9
| | | | | | using DIBuilder. llvm-svn: 139515
* Add DW_ATE_UTF, which clang started using in my previous commit!Devang Patel2011-09-121-0/+1
| | | | llvm-svn: 139503
* Remove the -compact-regions flag.Jakob Stoklund Olesen2011-09-121-11/+5
| | | | | | | It has been enabled by default for a while, it was only there to allow performance comparisons. llvm-svn: 139501
* Add an interface for SplitKit complement spill modes.Jakob Stoklund Olesen2011-09-123-5/+49
| | | | | | | | | | | | | | | | | | | | | | | | | SplitKit always computes a complement live range to cover the places where the original live range was live, but no explicit region has been allocated. Currently, the complement live range is created to be as small as possible - it never overlaps any of the regions. This minimizes register pressure, but if the complement is going to be spilled anyway, that is not very important. The spiller will eliminate redundant spills, and hoist others by making the spill slot live range overlap some of the regions created by splitting. Stack slots are cheap. This patch adds the interface to enable spill modes in SplitKit. In spill mode, SplitKit will assume that the complement is going to spill, so it will allow it to overlap regions in order to avoid back-copies. By doing some of the spiller's work early, the complement live range becomes simpler. In some cases, it can become much simpler because no extra PHI-defs are required. This will speed up both splitting and spilling. This is only the interface to enable spill modes, no implementation yet. llvm-svn: 139500
* Update comments to reflect some (not so) recent changes.Jakob Stoklund Olesen2011-09-121-4/+5
| | | | llvm-svn: 139498
* Associate a MemOperand with LDWCP nodes introduced during ISel.Richard Osborne2011-09-121-3/+8
| | | | | | This information is required if we want LDWCP to be hoisted out of loops. llvm-svn: 139495
* Mark LDWCP as having no side effects.Richard Osborne2011-09-121-1/+1
| | | | llvm-svn: 139494
* Format patterns, remove unused X86blend patternsNadav Rotem2011-09-122-27/+34
| | | | llvm-svn: 139491
* Fix disassembling of one of the register/register forms of ↵Craig Topper2011-09-111-0/+62
| | | | | | MOVUPS/MOVUPD/MOVAPS/MOVAPD/MOVSS/MOVSD and their VEX equivalents. Fixes PR10877. llvm-svn: 139486
* Fix disassembling of reverse register/register forms of ↵Craig Topper2011-09-111-4/+13
| | | | | | ADD/SUB/XOR/OR/AND/SBB/ADC/CMP/MOV. llvm-svn: 139485
* CR fixes per Bruno's request.Nadav Rotem2011-09-113-94/+48
| | | | | | | Undo the changes from r139285 which added custom lowering to vselect. Add tablegen lowering for vselect. llvm-svn: 139479
* r139454 activates an assert in a case where we were doing the right thing ↵Eli Friedman2011-09-101-1/+9
| | | | | | anyway. Make that explicit, and un-XFAIL the testcase. llvm-svn: 139458
* Fix the asserts in lib/Target/X86/X86ELFWriterInfo.cpp andRichard Trieu2011-09-102-2/+2
| | | | | | | | | | | | lib/ExecutionEngine/MCJIT/MCJIT.cpp from: assert("error"); to: assert(0 && "error"); llvm-svn: 139456
* Fixed an assert from:Richard Trieu2011-09-101-1/+1
| | | | | | | | | | | | | | assert("not implemented for target shuffle node"); to: assert(0 && "not implemented for target shuffle node"); This causes a test failure in CodeGen/X86/palignr.ll which has been marked as XFAIL for the time being. Test failure filed at PR10901. llvm-svn: 139454
* [disable-iv-rewrite] Allow WidenIV to handle NSW/NUW operationsAndrew Trick2011-09-101-1/+40
| | | | | | | | | | | | better. Don't immediately give up when an add operation can't be trivially sign/zero-extended within a loop. If it has NSW/NUW flags, generate a new expression with sign extended (non-recurrent) operand. As before, if SCEV says that all sign extends are loop invariant, then we can widen the operation. llvm-svn: 139453
* Set NSW/NUW flags on SCEVAddExpr when the operation is flagged asAndrew Trick2011-09-101-1/+7
| | | | | | | | | | such. I'm doing this now for completeness because I can't think of/remember any reason that it was left out. I'm not sure it will help anything, but if we don't do it we need to explain why in comments. llvm-svn: 139450
* Fix asserts in CodeGen from:Richard Trieu2011-09-102-3/+3
| | | | | | | | | | assert("error"); to: assert(0 && "error"); llvm-svn: 139449
* Thumb2 parsing and encoding for MOV(immediate).Jim Grosbach2011-09-102-4/+58
| | | | | | | Some aliases for MOV(register) also to keep existing T1 tests happy when run in thumbv7 mode. llvm-svn: 139440
* LDM writeback is not allowed if Rn is in the target register list.Owen Anderson2011-09-091-0/+19
| | | | llvm-svn: 139432
* Fix an ambiguously nested if.Owen Anderson2011-09-091-2/+2
| | | | llvm-svn: 139431
* Fix buildbot breakage caused by r139415. I missed one instance of a ↵Owen Anderson2011-09-091-1/+5
| | | | | | manually create ARM::tB. llvm-svn: 139429
* Fix assembly/disassembly of Thumb2 ADR instructions with immediate operands.Owen Anderson2011-09-093-2/+27
| | | | llvm-svn: 139422
* O64 will not be supported.Akira Hatanaka2011-09-092-2/+1
| | | | llvm-svn: 139421
* Make F31 and D15 non-reserved registers.Akira Hatanaka2011-09-092-5/+1
| | | | llvm-svn: 139420
* tidy up a bitChris Lattner2011-09-091-7/+5
| | | | llvm-svn: 139419
* Thumb unconditional branches are allowed in IT blocks, and therefore should ↵Owen Anderson2011-09-099-23/+70
| | | | | | have a predicate operand, unlike conditional branches. llvm-svn: 139415
* Mips32 does not reserve even-numbered floating point registers.Akira Hatanaka2011-09-091-5/+0
| | | | llvm-svn: 139412
* Make the SelectionDAG verify that all the operands of BUILD_VECTOR have the ↵Eli Friedman2011-09-092-24/+36
| | | | | | same type. Teach DAGCombiner::visitINSERT_VECTOR_ELT not to make invalid BUILD_VECTORs. Fixes PR10897. llvm-svn: 139407
* Drop support for Mips1 and Mips2.Akira Hatanaka2011-09-099-87/+6
| | | | llvm-svn: 139405
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