summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
...
* Revert "LiveRegUnits: Add accumulateBackward() function"Matthias Braun2017-01-202-42/+32
| | | | | | | | This seems to be breaking some bots. This reverts commit r292543. llvm-svn: 292574
* Revert "Demangle: only demangle mangled symbols"Saleem Abdulrasool2017-01-201-10/+1
| | | | | | | | This reverts SVN r286795. This was incorrect the demangler is expected to be able to demangle types as well as functions. This makes the behaviour of itaniumDemangle similar to __cxa_demangle once more. llvm-svn: 292573
* Revert "Recommit "[InlineCost] Use TTI to check if GEP is free.""Haicheng Wu2017-01-201-18/+2
| | | | | | This reverts commit r292570. The test still has problem. llvm-svn: 292572
* Recommit "[InlineCost] Use TTI to check if GEP is free."Haicheng Wu2017-01-201-2/+18
| | | | | | | | | | | | This recommits r292526 which is reverted in r292529 after fixing the test case. The original summary: Currently, a GEP is considered free only if its indices are all constant. TTI::getGEPCost() can give target-specific more accurate analysis. TTI is already used for the cost of many other instructions. llvm-svn: 292570
* [LoopInfo] Add helper methods to compute two useful orderings of theChandler Carruth2017-01-201-18/+4
| | | | | | | | | | | | | | | | | | | | | | loops in a function. These are relatively confusing to talk about and compute correctly so it seems really good to write down their implementation in one place. I've replaced one place we needed this in the loop PM infrastructure and I have another place in a pending patch that wants it. We can't quite use this for the core loop PM walk because there we're sometimes working on a sub-forest. I'll add the expected unittests before committing this but wanted to make sure folks were happy with these names / comments. Credit goes to Richard Smith for the idea for naming the order where siblings are in reverse program order but the tree traversal remains preorder. Differential Revision: https://reviews.llvm.org/D28932 llvm-svn: 292569
* [AArch64][GlobalISel] Widen scalar int->fp conversions.Ahmed Bougacha2017-01-202-1/+29
| | | | | | | It's incorrect to ignore the higher bits of the integer source. Teach the legalizer how to widen it. llvm-svn: 292563
* [AMDGPU] Prevent spills before exec mask is restoredStanislav Mekhanoshin2017-01-203-2/+15
| | | | | | | | | | | | | Inline spiller can decide to move a spill as early as possible in the basic block. It will skip phis and label, but we also need to make sure it skips instructions in the basic block prologue which restore exec mask. Added isPositionLike callback in TargetInstrInfo to detect instructions which shall be skipped in addition to common phis, labels etc. Differential Revision: https://reviews.llvm.org/D27997 llvm-svn: 292554
* GlobalISel: Add a note about how we're being a bit loose with memory operandsJustin Bogner2017-01-201-0/+4
| | | | | | | The logic in r292461 is conservatively correct, but we should revisit this later. Add a TODO so we don't forget. llvm-svn: 292553
* [MIRParser] Allow generic register specification on operand.Ahmed Bougacha2017-01-201-12/+16
| | | | | | | | This completes r292321 by adding support for generic registers, e.g.: %2:_(s32) = G_ADD %0, %1 llvm-svn: 292550
* GlobalISel: Only set FailedISel on dropped dbg intrinsics when using fallbackJustin Bogner2017-01-201-2/+2
| | | | | | | | | It's easier to test the non-fallback path if we just drop these intrinsics for now, like we did before we added the fallback path. We'll obviously need to fix this properly, but the fixme for that is already here. llvm-svn: 292547
* [AliasAnalysis] Fences do not modify constant memory locationAnna Thomas2017-01-201-0/+8
| | | | | | | | | | | | | | | | | | | Summary: Fence instructions are currently marked as `ModRef` for all memory locations. We can improve this for constant memory locations (such as constant globals), since fence instructions cannot modify these locations. This helps us to forward constant loads across fences (added test case in GVN). There were no changes in behaviour for similar test cases in early-cse and licm. Reviewers: dberlin, sanjoy, reames Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D28914 llvm-svn: 292546
* GlobalISel: Pass the MachineFunction in to reportSelectionError directlyJustin Bogner2017-01-201-6/+6
| | | | | | | | Rather than trying to find MF based on the possibly-null MI we've passed in here, just pass it in directly. It's already available at all callers anyway. llvm-svn: 292544
* LiveRegUnits: Add accumulateBackward() functionMatthias Braun2017-01-202-32/+42
| | | | | | | | | | | | | | | | This function can be used to accumulate the set of all read and modified register in a sequence of instructions. Use this code in AArch64A57FPLoadBalancing::scavengeRegister() to prove the concept. - The AArch64A57LoadBalancing code is using a backwards analysis now which is irrespective of kill flags. This is the main motivation for this change. Differential Revision: http://reviews.llvm.org/D22082 llvm-svn: 292543
* CodeGen: Add/Factor out LiveRegUnits class; NFCIMatthias Braun2017-01-203-59/+106
| | | | | | | | | | | | | This is a set of register units intended to track register liveness, it is similar in spirit to LivePhysRegs. You can also think of this as the liveness tracking parts of the RegisterScavenger factored out into an own class. This was proposed in http://llvm.org/PR27609 Differential Revision: http://reviews.llvm.org/D21916 llvm-svn: 292542
* AArch64: fall back to DAG ISel for inline assembly.Tim Northover2017-01-191-0/+3
| | | | | | | We can't currently handle "calls" to inlineasm strings so it's better to let the DAG handle it than generate rubbish. llvm-svn: 292540
* Fix a few more build errors.Zachary Turner2017-01-191-0/+2
| | | | llvm-svn: 292538
* Fix incorrectly formed assert statement.Zachary Turner2017-01-191-1/+1
| | | | llvm-svn: 292537
* [pdb] Add HashTable data structure.Zachary Turner2017-01-194-170/+331
| | | | | | | | | | | | | | | | This was being parsed / serialized ad-hoc inside the code for a specific PDB stream. But this data structure is used in multiple ways / places within the PDB format. To be able to re-use it we need to raise this code out and make it more generic. In doing so, a number of bugs are fixed in the original implementation, and support is added for growing the hash table and deleting items from the hash table, which had either been omitted or incorrect implemented in the initial version. Differential Revision: https://reviews.llvm.org/D28715 llvm-svn: 292535
* clang-format SampleProfile.cpp (NFC)Dehao Chen2017-01-191-6/+4
| | | | llvm-svn: 292533
* LTO: Flush the resolution file after writing to it.Peter Collingbourne2017-01-191-0/+1
| | | | | | Without this the file could be truncated if the linker crashes. llvm-svn: 292532
* [SCCP] Teach the pass how to handle `div` with overdefined operands.Davide Italiano2017-01-191-0/+6
| | | | | | | | | | | | | | | | | | This can prove that: extern int f; int g() { int x = 0; for (int i = 0; i < 365; ++i) { x /= f; } return x; } always returns zero. Thanks to Sanjoy for confirming this transformation actually made sense (bugs are mine). llvm-svn: 292531
* Revert "[InlineCost] Use TTI to check if GEP is free."Haicheng Wu2017-01-191-18/+2
| | | | | | This reverts commit r292526. The test case has problem. llvm-svn: 292529
* [SelectionDAG] Improve knownbits handling of UMIN/UMAX (PR31293)Simon Pilgrim2017-01-191-3/+33
| | | | | | | | | | | | This patch improves the knownbits logic for unsigned integer min/max opcodes. For UMIN we know that the result will have the maximum of the inputs' known leading zero bits in the result, similarly for UMAX the maximum of the inputs' leading one bits. This is particularly useful for simplifying clamping patterns,. e.g. as SSE doesn't have a uitofp instruction we want to use sitofp instead where possible and for that we need to confirm that the top bit is not set. Differential Revision: https://reviews.llvm.org/D28853 llvm-svn: 292528
* [InlineCost] Use TTI to check if GEP is free.Haicheng Wu2017-01-191-2/+18
| | | | | | | | | | Currently, a GEP is considered free only if its indices are all constant. TTI::getGEPCost() can give target-specific more accurate analysis. TTI is already used for the cost of many other instructions. Differential Revision: https://reviews.llvm.org/D28693 llvm-svn: 292526
* [AMDGPU] Add exec copy to LiveIntervals in SILowerControlFlow::emitElseStanislav Mekhanoshin2017-01-191-1/+3
| | | | | | | | | This instruction is missing from LiveIntervals. I'm not aware of any problems because of this though. Differential Revision: https://reviews.llvm.org/D28879 llvm-svn: 292521
* [libFuzzer] ensure that entries in PersistentAutoDictionary are not emptyKostya Serebryany2017-01-191-0/+3
| | | | llvm-svn: 292520
* [SCCP] Update comment in visitBinaryOp() after recent changes.Davide Italiano2017-01-191-3/+4
| | | | llvm-svn: 292519
* [XRay][Arm] Repair XRay table emission on Arm32 and add tests to identify ↵Serge Rogatch2017-01-191-0/+3
| | | | | | | | | | | | | | | | | | | such problem earlier Summary: Emission of XRay table was occasionally disabled for Arm32, but this bug was not then detected because earlier (also by mistake) testing of XRay was occasionally disabled on 32-bit Arm targets. This patch should fix that problem and detect such problems in the future. This patch is one of a series, see also - https://reviews.llvm.org/D28623 Reviewers: rengolin, dberris Reviewed By: dberris Subscribers: llvm-commits, aemerson, rengolin, dberris, iid_iunknown Differential Revision: https://reviews.llvm.org/D28624 llvm-svn: 292516
* [Assembler] Improve error when unable to evaluate expression.Chad Rosier2017-01-193-12/+13
| | | | | | | | | Add a SMLoc to MCExpr. Most code does not generate or consume the SMLoc (yet). Patch by Sanne Wouda <sanne.wouda@arm.com>! Differential Revision: https://reviews.llvm.org/D28861 llvm-svn: 292515
* Fix aliases to thumbfunc-based exprs to be thumbfunc.Evgeniy Stepanov2017-01-191-3/+9
| | | | | | | | | If F is a Thumb function symbol, and G = F + const, and G is a function symbol, then G is Thumb. Because what else could it be? Differential Revision: https://reviews.llvm.org/D28878 llvm-svn: 292514
* [libFuzzer] improve -minimize_crash: honor -artifact_prefix= and don't ↵Kostya Serebryany2017-01-195-12/+37
| | | | | | special case 2-byte inputs llvm-svn: 292511
* Improve what can be promoted in LICM.Xin Tong2017-01-191-6/+31
| | | | | | | | | | | | | | | | Summary: In case of non-alloca pointers, we check for whether it is a pointer from malloc-like calls and it is not captured. In such case, we can promote the pointer, as the caller will have no way to access this pointer even if there is unwinding in middle of the loop. Reviewers: hfinkel, sanjoy, reames, eli.friedman Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D28834 llvm-svn: 292510
* [libFuzzer] add two tests for experimenting with equivalence fuzzingKostya Serebryany2017-01-194-0/+46
| | | | llvm-svn: 292509
* Add an interface to scale the frequencies of a set of blocks.Easwaran Raman2017-01-191-0/+22
| | | | | | | | The scaling is done with reference to the the new frequency of a reference block. Differential Revision: https://reviews.llvm.org/D28535 llvm-svn: 292507
* [InstCombine] Simplify gep (gep p, a), (b-a)Davide Italiano2017-01-191-19/+13
| | | | | | | | Patch by Andrea Canciani. Differential Revision: https://reviews.llvm.org/D27413 llvm-svn: 292506
* [X86][SSE] Improve comments describing combineTruncatedArithmetic. NFCI.Simon Pilgrim2017-01-191-0/+7
| | | | llvm-svn: 292502
* Add support for the new LC_NOTE load command.Kevin Enderby2017-01-192-0/+41
| | | | | | | | | | It describes a region of arbitrary data included in a Mach-O file. Its initial use is to record extra data in MH_CORE files. rdar://30001545 rdar://30001731 llvm-svn: 292500
* [X86][SSE] Attempt to pre-truncate arithmetic operations that have already ↵Simon Pilgrim2017-01-191-6/+16
| | | | | | | | been extended As discussed on D28219 - it is profitable to combine trunc(binop (s/zext(x), s/zext(y)) to binop(trunc(s/zext(x)), trunc(s/zext(y))) assuming the trunc(ext()) will simplify further llvm-svn: 292493
* [InstCombine] icmp Pred (shl nsw X, C1), C0 --> icmp Pred X, C0 >> C1Sanjay Patel2017-01-191-24/+43
| | | | | | | | | | | | | | Try harder to fold icmp with shl nsw as discussed here: http://lists.llvm.org/pipermail/llvm-dev/2017-January/108749.html This is similar to the 'shl nuw' transforms that were added with D25913. This may eventually help solve: https://llvm.org/bugs/show_bug.cgi?id=30773 Differential Revision: https://reviews.llvm.org/D28406 llvm-svn: 292492
* [DAG] Don't increase SDNodeOrder for dbg.value/declare.Mikael Holmen2017-01-192-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: The SDNodeOrder is saved in the IROrder field in the SDNode, and this field may affects scheduling. Thus, letting dbg.value/declare increase the order numbers may in turn affect scheduling. Because of this change we also need to update the code deciding when dbg values should be output, in ScheduleDAGSDNodes.cpp/ProcessSDDbgValues. Dbg values now have the same order as the SDNode they are connected to, not the following orders. Test cases provided by Florian Hahn. Reviewers: bogner, aprantl, sunfish, atrick Reviewed By: atrick Subscribers: fhahn, probinson, andreadb, llvm-commits, MatzeB Differential Revision: https://reviews.llvm.org/D25318 llvm-svn: 292485
* Test commit access, remove trailing whitespaceMikael Holmen2017-01-191-1/+1
| | | | llvm-svn: 292482
* [GlobalISel] Pointers are legal operands for G_SELECT on AArch64Kristof Beyls2017-01-192-2/+2
| | | | | | Differential Revision: https://reviews.llvm.org/D28805 llvm-svn: 292481
* Recommiting unsigned saturation with a bugfix.Elena Demikhovsky2017-01-191-0/+100
| | | | | | | A test case that crached is added to avx512-trunc.ll. (PR31589) llvm-svn: 292479
* Re-commit: [globalisel] Tablegen-erate current Register Bank InformationDaniel Sanders2017-01-199-191/+88
| | | | | | | | | | | | | | | | | | | | | Summary: Adds a RegisterBank tablegen class that can be used to declare the register banks and an associated tablegen pass to generate the necessary code. Changes since first commit attempt: * Added missing guards * Added more missing guards * Found and fixed a use-after-free bug involving Twine locals Reviewers: t.p.northover, ab, rovka, qcolombet Reviewed By: qcolombet Subscribers: aditya_nandakumar, rengolin, kristof.beyls, vkalintiris, mgorny, dberris, llvm-commits, rovka Differential Revision: https://reviews.llvm.org/D27338 llvm-svn: 292478
* GlobalISel: Implement widening for shiftsJustin Bogner2017-01-191-5/+9
| | | | llvm-svn: 292476
* [AVX-512] Support ADD/SUB/MUL of mask vectorsCraig Topper2017-01-191-18/+19
| | | | | | | | | | | | | | | | | Summary: Currently we expand and scalarize these operations, but I think we should be able to implement ADD/SUB with KXOR and MUL with KAND. We already do this for scalar i1 operations so I just extended it to vectors of i1. Reviewers: zvi, delena Reviewed By: delena Subscribers: guyblank, llvm-commits Differential Revision: https://reviews.llvm.org/D28888 llvm-svn: 292474
* AMDGPU: Disable some fneg combines unless nszMatt Arsenault2017-01-192-0/+16
| | | | | | | | | | | | For -(x + y) -> (-x) + (-y), if x == -y, this would change the result from -0.0 to 0.0. Since the fma/fmad combine is an extension of this problem it also applies there. fmul should be fine, and I don't think any of the unary operators or conversions should be a problem either. llvm-svn: 292473
* AMDGPU: Remove modifiers from v_div_scale_*Matt Arsenault2017-01-192-9/+7
| | | | | | | | They seem to produce nonsense results when used. This should be applied to the release branch. llvm-svn: 292472
* [X86] Merge LowerADD and LowerSUB into a single LowerADD_SUB since they are ↵Craig Topper2017-01-191-13/+3
| | | | | | identical. llvm-svn: 292469
* [AVX-512] Use VSHUF instructions instead of two inserts as fallback for ↵Craig Topper2017-01-191-78/+33
| | | | | | subvector broadcasts that can't fold the load. llvm-svn: 292466
OpenPOWER on IntegriCloud