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authorStanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com>2017-01-19 21:26:22 +0000
committerStanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com>2017-01-19 21:26:22 +0000
commit68257700f8802b94a882f3c9e60b813bc8278983 (patch)
treead3bcf91fd19ff59eccd1602ff52774aeca6402f /llvm/lib
parenta44ebf4d065478d3042da45b9d0f7c3060da3b65 (diff)
downloadbcm5719-llvm-68257700f8802b94a882f3c9e60b813bc8278983.tar.gz
bcm5719-llvm-68257700f8802b94a882f3c9e60b813bc8278983.zip
[AMDGPU] Add exec copy to LiveIntervals in SILowerControlFlow::emitElse
This instruction is missing from LiveIntervals. I'm not aware of any problems because of this though. Differential Revision: https://reviews.llvm.org/D28879 llvm-svn: 292521
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp4
1 files changed, 3 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp b/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
index 4a7dff44dfc..0a0faf36c22 100644
--- a/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
+++ b/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
@@ -219,7 +219,8 @@ void SILowerControlFlow::emitElse(MachineInstr &MI) {
// tied. In order to correctly tie the registers, split this into a copy of
// the src like it does.
unsigned CopyReg = MRI->createVirtualRegister(&AMDGPU::SReg_64RegClass);
- BuildMI(MBB, Start, DL, TII->get(AMDGPU::COPY), CopyReg)
+ MachineInstr *CopyExec =
+ BuildMI(MBB, Start, DL, TII->get(AMDGPU::COPY), CopyReg)
.add(MI.getOperand(1)); // Saved EXEC
// This must be inserted before phis and any spill code inserted before the
@@ -261,6 +262,7 @@ void SILowerControlFlow::emitElse(MachineInstr &MI) {
LIS->RemoveMachineInstrFromMaps(MI);
MI.eraseFromParent();
+ LIS->InsertMachineInstrInMaps(*CopyExec);
LIS->InsertMachineInstrInMaps(*OrSaveExec);
LIS->InsertMachineInstrInMaps(*Xor);
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