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* DebugLoc's don't hide any interesting types for TypeFinder to find.Chris Lattner2011-07-141-1/+1
| | | | llvm-svn: 135174
* manually copy debugloc over to a new instruction in clone() insteadChris Lattner2011-07-141-1/+3
| | | | | | | of calling getAllMetadata(). This is semantically identical, but doing it this way avoids unpacking the DebugLoc. llvm-svn: 135173
* Stop the ValueMapper from calling getAllMetadata, which unpacks DebugLoc intoChris Lattner2011-07-141-2/+3
| | | | | | | an MDNode. This saves a bunch of time and memory in the IR linker, e.g. when doing LTO of files with debug info. llvm-svn: 135172
* Add 256-bit load/store recognition and matching in several places.Bruno Cardoso Lopes2011-07-142-4/+74
| | | | llvm-svn: 135171
* Don't leak operands when putting them into a shift.Benjamin Kramer2011-07-141-1/+1
| | | | llvm-svn: 135169
* Update ARM Assembly of LDM/STM.Jim Grosbach2011-07-141-5/+8
| | | | | | | ldm/stm are the cannonical spellings for ldmia/stmia, so use them as such. Update the parsing/encoding tests accordingly. llvm-svn: 135168
* add comments.Chris Lattner2011-07-141-1/+3
| | | | llvm-svn: 135164
* consolidate GlobalValue::isDeclaration into one Chris Lattner2011-07-141-8/+13
| | | | | | non-virtual function. llvm-svn: 135163
* code cleanupChris Lattner2011-07-141-20/+15
| | | | llvm-svn: 135157
* ARM ISB instruction assembly parsing.Jim Grosbach2011-07-142-3/+7
| | | | | | | The ISB instruction takes an optional operand, just like DMB/DSB. Typically only 'sy' is meaningful. llvm-svn: 135156
* Change Intrinsic::getDeclaration and friends to take an ArrayRef.Benjamin Kramer2011-07-149-23/+18
| | | | llvm-svn: 135154
* add a couple more missing C api, patch by Vitaly Lugovskiy!Chris Lattner2011-07-141-0/+8
| | | | llvm-svn: 135151
* Update XCoreRegisterInfo::eliminateFrameIndex() to handle DBG_VALUERichard Osborne2011-07-141-9/+17
| | | | | | instructions. llvm-svn: 135146
* Simplify some functions in the C API by using an ArrayRef to directly ↵Frits van Bommel2011-07-141-13/+3
| | | | | | reference the array passed to them instead of copying it to a std::vector. llvm-svn: 135145
* [VECTOR-SELECT]Nadav Rotem2011-07-143-3/+66
| | | | | | | | | | | During type legalization we often use the SIGN_EXTEND_INREG SDNode. When this SDNode is legalized during the LegalizeVector phase, it is scalarized because non-simple types are automatically marked to be expanded. In this patch we add support for lowering SIGN_EXTEND_INREG manually. This fixes CodeGen/X86/vec_sext.ll when running with the '-promote-elements' flag. llvm-svn: 135144
* Add assertion for the chain value typeNadav Rotem2011-07-141-0/+10
| | | | llvm-svn: 135143
* add C api for hte new type system rewrite API. Patch by Vitaly Lugovskiy!Chris Lattner2011-07-141-0/+13
| | | | llvm-svn: 135132
* Unfortunately several files in MC are badly violating layering rule by usingEvan Cheng2011-07-148-16/+23
| | | | | | | | | TargetAsmInfo, which in turn pulls in TargetRegisterInfo, etc. :-( There are other cases of violations, but this is probably the worst. This patch is but one small step towards fixing this. 500 more steps to go. :-( llvm-svn: 135131
* Reapply r135121 with a fixed copy constructor.Jakob Stoklund Olesen2011-07-143-11/+70
| | | | | | | | | | | | | | | | | | | | | Original commit message: Count references to interference cache entries. Each InterferenceCache::Cursor instance references a cache entry. A non-zero reference count guarantees that the entry won't be reused for a new register. This makes it possible to have multiple live cursors examining interference for different physregs. The total number of live cursors into a cache must be kept below InterferenceCache::getMaxCursors(). Code generation should be unaffected by this change, and it doesn't seem to affect the cache replacement strategy either. llvm-svn: 135130
* Simplify.Devang Patel2011-07-141-13/+3
| | | | llvm-svn: 135127
* Don't emit a bit test if there is only one case the test can yield false. A ↵Benjamin Kramer2011-07-142-10/+13
| | | | | | simple SETNE is sufficient. llvm-svn: 135126
* Simplify and delay extracting DebugLoc elements, scope and InlinedAt, as ↵Devang Patel2011-07-143-18/+30
| | | | | | much as possible. llvm-svn: 135124
* Add a dag combine pattern for folding C2-(A+C1) -> (C2-C1)-AEric Christopher2011-07-141-2/+10
| | | | | | Fixes rdar://9761830 llvm-svn: 135123
* Revert r135121 which broke a gcc-4.2 builder.Jakob Stoklund Olesen2011-07-143-70/+11
| | | | llvm-svn: 135122
* Count references to interference cache entries.Jakob Stoklund Olesen2011-07-143-11/+70
| | | | | | | | | | | | | | | | | Each InterferenceCache::Cursor instance references a cache entry. A non-zero reference count guarantees that the entry won't be reused for a new register. This makes it possible to have multiple live cursors examining interference for different physregs. The total number of live cursors into a cache must be kept below InterferenceCache::getMaxCursors(). Code generation should be unaffected by this change, and it doesn't seem to affect the cache replacement strategy either. llvm-svn: 135121
* Fix up assertion in r135018 so it doesn't trigger on 32-bit; when we're in ↵Eli Friedman2011-07-141-1/+2
| | | | | | 32-bit, it doesn't matter whether the operation overflows because the computed address is not wider than the immediate. llvm-svn: 135120
* Simplify. Compile unit check inside hasValidLocation() did not add any value.Devang Patel2011-07-141-26/+10
| | | | llvm-svn: 135118
* ARM Assembler support for DSB instruction.Jim Grosbach2011-07-141-0/+2
| | | | | | Add instalias for default 'sy' option. Add tests. llvm-svn: 135116
* Reapply r135074 and r135080 with a fix.Jakob Stoklund Olesen2011-07-142-28/+39
| | | | | | | | | | The cache entry referenced by the best split candidate could become clobbered by an unsuccessful candidate. The correct fix here is to use reference counts on the cache entries. Coming up. llvm-svn: 135113
* DMB instalias needs the same predicate as the instruction.Jim Grosbach2011-07-141-1/+1
| | | | llvm-svn: 135112
* Fix typo in DEBUG message.Devang Patel2011-07-141-2/+2
| | | | llvm-svn: 135111
* Add DEBUG messages.Devang Patel2011-07-141-0/+5
| | | | llvm-svn: 135110
* ARM Assembler support for DMB instruction.Jim Grosbach2011-07-132-0/+6
| | | | | | | | Flesh out the options supported for the instruction. Shuffle tests a bit and add entries for the rest of the options. Add an alias to handle the default operand of "sy". llvm-svn: 135109
* Update comments. These are for assembler, too.Jim Grosbach2011-07-131-3/+2
| | | | llvm-svn: 135107
* Add a target-indepedent entry to MCInstrDesc to describe the encoded size of ↵Owen Anderson2011-07-138-246/+213
| | | | | | an opcode. Switch ARM over to using that rather than its own special MCInstrDesc bits. llvm-svn: 135106
* Add code to handle a "frameless" unwind stack.Bill Wendling2011-07-131-13/+55
| | | | | | | The frameless unwind stack has a special encoding, the algorithm for which is in "permuteEncode". llvm-svn: 135103
* ARM Assembler support for DBG instruction.Jim Grosbach2011-07-132-5/+3
| | | | | | Add range checking and testing for parsing and encoding of DBG instruction. llvm-svn: 135102
* Revert r135074 and r135080. They broke clamscan.Jakob Stoklund Olesen2011-07-132-34/+28
| | | | llvm-svn: 135096
* Revert 135093. Think-o.Jim Grosbach2011-07-131-2/+2
| | | | llvm-svn: 135094
* Correct range for thumb co-processor immediateJim Grosbach2011-07-131-2/+2
| | | | llvm-svn: 135093
* Range checking for CDP[2] immediates.Jim Grosbach2011-07-134-12/+50
| | | | llvm-svn: 135092
* Make X86ISD::ANDNP more general and Codegen 256-bit VANDNP. A moreBruno Cardoso Lopes2011-07-133-64/+37
| | | | | | | general version of X86ISD::ANDNP also opened the room for a little bit of refactoring. llvm-svn: 135088
* The target specific node PANDN name is misleading. That happens becauseBruno Cardoso Lopes2011-07-134-12/+12
| | | | | | | it's later selected to a ANDNPD/ANDNPS instruction instead of the PANDN instruction. Rename it. llvm-svn: 135087
* Cleanup Thumb co-processor instructions a bit.Jim Grosbach2011-07-131-79/+35
| | | | | | Combine redundant base classes and such. No indended functional change. llvm-svn: 135085
* Make sure we don't combine a large displacement and a frame index in the ↵Eli Friedman2011-07-131-8/+25
| | | | | | | | same addressing mode on x86-64. It can overflow, leading to a crash/miscompile. <rdar://problem/9763308> llvm-svn: 135084
* Parameterize away the ARM T1Cop class.Jim Grosbach2011-07-132-13/+12
| | | | llvm-svn: 135082
* Fix predicates for Thumb co-processor instructions.Jim Grosbach2011-07-133-104/+95
| | | | | | | They're all Thumb2 only, not just some of them. More refactoring cleanup coming. llvm-svn: 135081
* Only keep the global split candidates that work out.Jakob Stoklund Olesen2011-07-131-12/+15
| | | | | | | | | Some pysical registers create split solutions that would spill anywhere. They should not even be considered in future multi-way global splits. This does not affect code generation (yet). llvm-svn: 135080
* Refactor out checking for displacements on x86-64 addressing modes. No ↵Eli Friedman2011-07-131-46/+34
| | | | | | | | functionality change. Refactoring in preparation for an additional safety check in FoldOffsetIntoAddress. Part of <rdar://problem/9763308>. llvm-svn: 135079
* Fix encoding for ARM BXJ instruction.Jim Grosbach2011-07-131-3/+5
| | | | llvm-svn: 135077
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