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* remove the DerivedType which isn't adding value anymore.Chris Lattner2011-07-092-3/+2
| | | | llvm-svn: 134832
* Land the long talked about "type system rewrite" patch. ThisChris Lattner2011-07-0941-4403/+2365
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | patch brings numerous advantages to LLVM. One way to look at it is through diffstat: 109 files changed, 3005 insertions(+), 5906 deletions(-) Removing almost 3K lines of code is a good thing. Other advantages include: 1. Value::getType() is a simple load that can be CSE'd, not a mutating union-find operation. 2. Types a uniqued and never move once created, defining away PATypeHolder. 3. Structs can be "named" now, and their name is part of the identity that uniques them. This means that the compiler doesn't merge them structurally which makes the IR much less confusing. 4. Now that there is no way to get a cycle in a type graph without a named struct type, "upreferences" go away. 5. Type refinement is completely gone, which should make LTO much MUCH faster in some common cases with C++ code. 6. Types are now generally immutable, so we can use "Type *" instead "const Type *" everywhere. Downsides of this patch are that it removes some functions from the C API, so people using those will have to upgrade to (not yet added) new API. "LLVM 3.0" is the right time to do this. There are still some cleanups pending after this, this patch is large enough as-is. llvm-svn: 134829
* Windows/DynamicLibrary.inc: Fix trivial warnings. Thanks to John Myers!NAKAMURA Takumi2011-07-092-3/+3
| | | | llvm-svn: 134812
* Revert accidental commit.Evan Cheng2011-07-091-6/+0
| | | | llvm-svn: 134800
* Change createAsmParser to take a MCSubtargetInfo instead of triple,Evan Cheng2011-07-0923-56/+263
| | | | | | | | | CPU, and feature string. Parsing some asm directives can change subtarget state (e.g. .code 16) and it must be reflected in other modules (e.g. MCCodeEmitter). That is, the MCSubtargetInfo instance must be shared. llvm-svn: 134795
* Oops, didn't mean to commit that.Jakob Stoklund Olesen2011-07-091-1/+1
| | | | | | | | Spills should be hoisted out of loops, but we don't want to hoist them to dominating blocks at the same loop depth. That could cause the spills to be executed more often. llvm-svn: 134782
* Added recognition for signed add/sub/mul with overflow intrinsics to GVN as ↵Lang Hames2011-07-091-0/+3
| | | | | | per Chris and Frits suggestion. llvm-svn: 134777
* Hoist spills within a basic block.Jakob Stoklund Olesen2011-07-091-3/+28
| | | | | | | | | | Try to move spills as early as possible in their basic block. This can help eliminate interferences by shortening the live range being spilled. This fixes PR10221. llvm-svn: 134776
* Really force on 64bit for 64-bit targets. Should fix remaining failures on ↵Eli Friedman2011-07-081-3/+11
| | | | | | unknown x86/non-x86 targets. llvm-svn: 134773
* Revert earlier unnecessary hack. Make sure we correctly force on 64bit and ↵Eli Friedman2011-07-082-4/+9
| | | | | | cmov for 64-bit targets. llvm-svn: 134768
* Fix indentation.Evan Cheng2011-07-081-2/+2
| | | | llvm-svn: 134764
* Fix comment.Evan Cheng2011-07-081-1/+1
| | | | llvm-svn: 134763
* Add support for ARM / Thumb mode switching with .code 16 and .code 32.Evan Cheng2011-07-081-16/+30
| | | | llvm-svn: 134760
* Update comments for SandyBridge CPU identifiers.Bob Wilson2011-07-081-2/+6
| | | | llvm-svn: 134759
* Mark tBRIND as predicable.Jim Grosbach2011-07-081-2/+2
| | | | llvm-svn: 134758
* Restore old behavior. Always auto-detect features unless cpu or features are ↵Evan Cheng2011-07-083-20/+7
| | | | | | specified. llvm-svn: 134757
* Pseudo-ize tBRIND.Jim Grosbach2011-07-081-12/+6
| | | | llvm-svn: 134755
* Default 64-bit target features and SSE2 on when a triple specifies x86-64. ↵Eli Friedman2011-07-082-37/+1
| | | | | | Clean up all the other hacks which are now unnecessary. llvm-svn: 134753
* Recognize Intel CPUs with Family=6 and Model=44.Bob Wilson2011-07-081-0/+1
| | | | | | | | According to Intel Application Note 485, this value is used for "Intel Core i7 and Intel Xeon processor". Just include it with the other "corei7-avx" entries. llvm-svn: 134750
* Reapply a fixed version of r133285.Bob Wilson2011-07-081-5/+8
| | | | | | | This tightens up checking for overflow in alloca sizes, based on feedback from Duncan and John about the change in r132926. llvm-svn: 134749
* Make tBX_RET and tBX_RET_vararg predicable.Jim Grosbach2011-07-083-7/+10
| | | | | | | | | | The normal tBX instruction is predicable, so there's no reason the pseudos for using it as a return shouldn't be. Gives us some nice code-gen improvements as can be seen by the test changes. In particular, several tests now have to disable if-conversion because it works too well and defeats the test. llvm-svn: 134746
* Add _allrem, _aullrem and _allmul to the runtime for MSVC.Julien Lerouge2011-07-081-0/+6
| | | | | | http://llvm.org/bugs/show_bug.cgi?id=10305 llvm-svn: 134744
* Add an intrinsic and codegen support for fused multiply-accumulate. The intentCameron Zwarich2011-07-0815-0/+70
| | | | | | is to use this for architectures that have a native FMA instruction. llvm-svn: 134742
* For non-x86 host, used generic as CPU name.Evan Cheng2011-07-082-6/+16
| | | | llvm-svn: 134741
* Pseudo-ize tBX_RET and tBX_RET_vararg.Jim Grosbach2011-07-081-16/+5
| | | | llvm-svn: 134739
* Plug a leak by giving the AsmParser ownership of the MCSubtargetInfo.Benjamin Kramer2011-07-082-6/+8
| | | | | | Found by valgrind. llvm-svn: 134738
* Shuffle productions around a bit.Jim Grosbach2011-07-081-21/+21
| | | | | | No functional change. llvm-svn: 134737
* Be more aggressive about following hints.Jakob Stoklund Olesen2011-07-084-66/+149
| | | | | | | | | | | | | | | | | | | | RAGreedy::tryAssign will now evict interference from the preferred register even when another register is free. To support this, add the EvictionCost struct that counts how many hints are broken by an eviction. We don't want to break one hint just to satisfy another. Rename canEvict to shouldEvict, and add the first bit of eviction policy that doesn't depend on spill weights: Always make room in the preferred register as long as the evictees can be split and aren't already assigned to their preferred register. Also make the CSR avoidance more accurate. When looking for a cheaper register it is OK to use a new volatile register. Only CSR aliases that have never been used before should be avoided. llvm-svn: 134735
* Use tPseudoExpand for tTAILJMPrND and tTAILJMPr.Jim Grosbach2011-07-082-20/+8
| | | | llvm-svn: 134734
* Use tPseudoExpand for tTAILJMPd and tTAILJMPdND.Jim Grosbach2011-07-083-18/+17
| | | | llvm-svn: 134732
* Silence compiler warning.Benjamin Kramer2011-07-081-0/+2
| | | | llvm-svn: 134730
* Add more info to FIXME.Jim Grosbach2011-07-081-1/+5
| | | | llvm-svn: 134729
* Move Thumb tail call pseudos to Thumb.td file.Jim Grosbach2011-07-082-15/+25
| | | | | | Fix a FIXME. llvm-svn: 134727
* TargetAsmParser doesn't need reference to Target.Evan Cheng2011-07-084-11/+10
| | | | llvm-svn: 134721
* Remove unused copy of UpdateInlinedAtInfo.Benjamin Kramer2011-07-081-12/+0
| | | | llvm-svn: 134720
* Use ARMPseudoExpand for ARM tail calls.Jim Grosbach2011-07-082-31/+17
| | | | llvm-svn: 134719
* Shuffle productions around a bit.Jim Grosbach2011-07-081-55/+59
| | | | | | No functional change. llvm-svn: 134714
* Use ARMPseudoExpand for BLr9, BLr9_pred, BXr9, and BXr9_pred.Jim Grosbach2011-07-082-28/+15
| | | | | | TableGen'erated MC lowering pseudo-expansion. llvm-svn: 134712
* Refactor. It is inliner's responsibility to update line number information.Devang Patel2011-07-082-38/+40
| | | | llvm-svn: 134708
* Add CMake support for the new TableGen file introduced in r134705.Chandler Carruth2011-07-081-0/+1
| | | | llvm-svn: 134707
* Use TableGen'erated pseudo lowering for ARM.Jim Grosbach2011-07-088-211/+191
| | | | | | | | | Hook up the TableGen lowering for simple pseudo instructions for ARM and use it for a subset of the many pseudos the backend has as proof of concept. More conversions to come. llvm-svn: 134705
* Refactor.Devang Patel2011-07-081-28/+29
| | | | llvm-svn: 134703
* Make provision to have floating point constants in .debug_loc expressions.Devang Patel2011-07-082-43/+80
| | | | llvm-svn: 134702
* Apparently we can't expect a BinaryOperator here.Benjamin Kramer2011-07-081-2/+2
| | | | | | Should fix llvm-gcc selfhost. llvm-svn: 134699
* Emit a more efficient magic number multiplication for exact sdivs.Benjamin Kramer2011-07-083-1/+43
| | | | | | | | | | | | | | | | | | | | | | | | We have to do this in DAGBuilder instead of DAGCombiner, because the exact bit is lost after building. struct foo { char x[24]; }; long bar(struct foo *a, struct foo *b) { return a-b; } is now compiled into movl 4(%esp), %eax subl 8(%esp), %eax sarl $3, %eax imull $-1431655765, %eax, %eax instead of movl 4(%esp), %eax subl 8(%esp), %eax movl $715827883, %ecx imull %ecx movl %edx, %eax shrl $31, %eax sarl $2, %edx addl %eax, %edx movl %edx, %eax llvm-svn: 134695
* Eliminate asm parser's dependency on TargetMachine:Evan Cheng2011-07-0842-197/+235
| | | | | | | | | | - Each target asm parser now creates its own MCSubtatgetInfo (if needed). - Changed AssemblerPredicate to take subtarget features which tablegen uses to generate asm matcher subtarget feature queries. e.g. "ModeThumb,FeatureThumb2" is translated to "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0". llvm-svn: 134678
* Make GVN look through extractvalues for recognised intrinsics. GVN can then ↵Lang Hames2011-07-081-7/+54
| | | | | | CSE ops that match values produced by the intrinsics. llvm-svn: 134677
* Raise assertion when MachineOperand has unexpected target flag.Akira Hatanaka2011-07-081-1/+2
| | | | llvm-svn: 134671
* Make sure variable Kind is assigned a value to suppress warning.Akira Hatanaka2011-07-081-1/+1
| | | | llvm-svn: 134668
* Let the inline asm 'q' constraint match float, and on 64-bit double too.Nick Lewycky2011-07-081-3/+3
| | | | | | Fixes PR9602! llvm-svn: 134665
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