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* Recommit r358887 "[TargetLowering][AMDGPU][X86] Improve SimplifyDemandedBits ↵Craig Topper2019-05-133-1/+45
| | | | | | | | | | | | | | | | | | | | bitcast handling" I've included a new fix in X86RegisterInfo to prevent PR41619 without reintroducing r359392. We might be able to improve that in the base class implementation of shouldRewriteCopySrc somehow. But this hopefully enables forward progress on SimplifyDemandedBits improvements for now. Original commit message: This patch adds support for BigBitWidth -> SmallBitWidth bitcasts, splitting the DemandedBits/Elts accordingly. The AMDGPU backend needed an extra (srl (and x, c1 << c2), c2) -> (and (srl(x, c2), c1) combine to encourage BFE creation, I investigated putting this in DAGComb but it caused a lot of noise on other targets - some improvements, some regressions. The X86 changes are all definite wins. llvm-svn: 360552
* [WebAssembly] Move InstPrinter files to MCTargetDesc. NFCDavid L. Jones2019-05-1313-40/+15
| | | | | | | | | For some targets, there is a circular dependency between InstPrinter and MCTargetDesc. Merging them together will fix this. For the other targets, the merging is to maintain consistency so all targets will have the same structure. llvm-svn: 360550
* [JITLink] Add a test for zero-filled content.Lang Hames2019-05-122-12/+26
| | | | | | | | Also updates RuntimeDyldChecker and llvm-rtdyld to support zero-fill tests by returning a content address of zero (but no error) for zero-fill atoms, and treating loads from zero as returning zero. llvm-svn: 360547
* [X86][AVX] Split VZEXT_MOVL ymm/zmm if the upper elements are not demanded.Simon Pilgrim2019-05-121-0/+12
| | | | | | Removes unnecessary vzeroupper noted in D61806 llvm-svn: 360543
* [DAGCombiner] try to move bitcast after extract_subvectorSanjay Patel2019-05-121-0/+24
| | | | | | | | | | | | | | | | | I noticed that we were failing to narrow an x86 ymm math op in a case similar to the 'madd' test diff. That is because a bitcast is sitting between the math and the extract subvector and thwarting our pattern matching for narrowing: t56: v8i32 = add t59, t58 t68: v4i64 = bitcast t56 t73: v2i64 = extract_subvector t68, Constant:i64<2> t96: v4i32 = bitcast t73 There are a few wins and neutral diffs in the other tests. Differential Revision: https://reviews.llvm.org/D61806 llvm-svn: 360541
* [X86][SSE] SimplifyDemandedBits - call PEXTRB/PEXTRW ↵Simon Pilgrim2019-05-111-1/+6
| | | | | | | | | | SimplifyDemandedVectorElts as well. See if we can simplify the demanded vector elts from the extraction before trying to simplify the demanded bits. This helps us with target shuffles and hops in particular. llvm-svn: 360535
* [DAG] Add SimplifyDemandedBits support for BITREVERSESimon Pilgrim2019-05-111-0/+10
| | | | | | Pulled out of D58017 while I continue to investigate the BSWAP regression on PPC llvm-svn: 360534
* [CommandLine] Add long option flag for cl::ParseCommandLineOptions . Part 5 of 5Don Hinton2019-05-111-20/+40
| | | | | | | | | | | | | | | | | | | Summary: If passed, the long option flag makes the CommandLine parser mimic the behavior or GNU getopt_long. Short options are a single character prefixed by a single dash, and long options are multiple characters prefixed by a double dash. This patch was motivated by the discussion in the following thread: http://lists.llvm.org/pipermail/llvm-dev/2019-April/131786.html Reviewed By: MaskRay Tags: #llvm Differential Revision: https://reviews.llvm.org/D61294 llvm-svn: 360532
* [CostModel][X86] Add min/max reduction costs for all SSE targetsSimon Pilgrim2019-05-111-6/+90
| | | | | | | | The original costs stopped at SSE42, I've added conservative estimates for everything down to SSE1/SSE2 and moved some of the SSE42 costs to SSE41 (really only the addition of PCMPGT makes any difference). I've also added missing vXi8 costs (we use PHMINPOSUW for i8/i16 for scarily quick results) and 256-bit vector costs for AVX1. llvm-svn: 360528
* [X86][SSE] Add SimplifyDemandedVectorElts HADD/HSUB handling.Simon Pilgrim2019-05-111-0/+45
| | | | | | Still missing PHADDW/PHSUBW tests because PEXTRW doesn't call SimplifyDemandedVectorElts llvm-svn: 360526
* FixupLEAPass::fixupIncDec - non-LEA opcodes should not happen here. NFCI.Simon Pilgrim2019-05-111-0/+2
| | | | | | Matches what we do in other functions and fixes scan-build warning about uninitialized NewOpcode variable. llvm-svn: 360525
* [X86] Add CMOV_FR32X/CMOV_FR64X pseudo instructions. Use them in fast isel ↵Craig Topper2019-05-113-4/+14
| | | | | | | | to fix a machine verifier error after adding test cases. Fast isel picks the FR32X/FR64X register classes when lowering pseudo select, but it didn't have the right opcode to go with it. llvm-svn: 360524
* [X86] Sink some fast isel code into the only if that uses it. NFCCraig Topper2019-05-111-13/+13
| | | | llvm-svn: 360523
* [X86] Use TLI.getRegClassFor to simplify some more fast isel code. NFCICraig Topper2019-05-111-16/+7
| | | | llvm-svn: 360522
* HexagonConstEvaluator::evaluateHexExt - check incoming opcodes. NFCI.Simon Pilgrim2019-05-111-0/+2
| | | | | | Only certain extension opcodes are supported - fixes scan build warning. llvm-svn: 360520
* Fix uninitialized variable analyzer warning. NFCI.Simon Pilgrim2019-05-111-1/+1
| | | | llvm-svn: 360516
* SelectionDAGISel::CodeGenAndEmitDAG - remove unused variable. NFCI.Simon Pilgrim2019-05-111-3/+0
| | | | llvm-svn: 360514
* [X86] Use getRegClassFor to simplify some code in fast isel. NFCICraig Topper2019-05-111-40/+18
| | | | | | | No need to select the register class based on type and features. It should already be setup by X86ISelLowering. llvm-svn: 360513
* [X86] Don't emit MOVNTDQA loads from fast-isel without SSE4.1.Craig Topper2019-05-111-1/+1
| | | | | | | | We were checking for SSE4.1 for FP types, but not integer 128-bit types. Fixes PR41837. llvm-svn: 360512
* [X86] Add a test case for idempotent atomic operations with speculative load ↵Craig Topper2019-05-111-1/+3
| | | | | | | | hardening. Fix an additional issue found by the test. This test covers the fix from r360475 as well. llvm-svn: 360511
* [SystemZ] Move InstPrinter files to MCTargetDesc. NFCRichard Trieu2019-05-1112-36/+11
| | | | | | | | | For some targets, there is a circular dependency between InstPrinter and MCTargetDesc. Merging them together will fix this. For the other targets, the merging is to maintain consistency so all targets will have the same structure. llvm-svn: 360510
* [Sparc] Move InstPrinter files to MCTargetDesc. NFCRichard Trieu2019-05-1111-34/+9
| | | | | | | | | For some targets, there is a circular dependency between InstPrinter and MCTargetDesc. Merging them together will fix this. For the other targets, the merging is to maintain consistency so all targets will have the same structure. llvm-svn: 360506
* [RISCV] Move InstPrinter files to MCTargetDesc. NFCRichard Trieu2019-05-1110-33/+8
| | | | | | | | | For some targets, there is a circular dependency between InstPrinter and MCTargetDesc. Merging them together will fix this. For the other targets, the merging is to maintain consistency so all targets will have the same structure llvm-svn: 360505
* [PowerPC] Move InstPrinter files to MCTargetDesc. NFCRichard Trieu2019-05-1110-34/+9
| | | | | | | | | For some targets, there is a circular dependency between InstPrinter and MCTargetDesc. Merging them together will fix this. For the other targets, the merging is to maintain consistency so all targets will have the same structure. llvm-svn: 360502
* [NVPTX] Move InstPrinter files to MCTargetDesc. NFCRichard Trieu2019-05-1110-34/+9
| | | | | | | | | For some targets, there is a circular dependency between InstPrinter and MCTargetDesc. Merging them together will fix this. For the other targets, the merging is to maintain consistency so all targets will have the same structure. llvm-svn: 360500
* [MSP430] Move InstPrinter files to MCTargetDesc. NFCRichard Trieu2019-05-1110-33/+8
| | | | | | | | | For some targets, there is a circular dependency between InstPrinter and MCTargetDesc. Merging them together will fix this. For the other targets, the merging is to maintain consistency so all targets will have the same structure. llvm-svn: 360498
* [Mips] Move InstPrinter files to MCTargetDesc. NFCRichard Trieu2019-05-1113-37/+11
| | | | | | | | | For some targets, there is a circular dependency between InstPrinter and MCTargetDesc. Merging them together will fix this. For the other targets, the merging is to maintain consistency so all targets will have the same structure. llvm-svn: 360497
* [Lanai] Move InstPrinter files to MCTargetDesc. NFCRichard Trieu2019-05-1110-35/+9
| | | | | | | | | For some targets, there is a circular dependency between InstPrinter and MCTargetDesc. Merging them together will fix this. For the other targets, the merging is to maintain consistency so all targets will have the same structure. llvm-svn: 360496
* [BPF] Move InstPrinter files to MCTargetDesc. NFCRichard Trieu2019-05-1110-34/+8
| | | | | | | | | For some targets, there is a circular dependency between InstPrinter and MCTargetDesc. Merging them together will fix this. For the other targets, the merging is to maintain consistency so all targets will have the same structure. llvm-svn: 360494
* [AVR] Move InstPrinter files to MCTargetDesc. NFCRichard Trieu2019-05-1110-36/+6
| | | | | | | | | For some targets, there is a circular dependency between InstPrinter and MCTargetDesc. Merging them together will fix this. For the other targets, the merging is to maintain consistency so all targets will have the same structure. llvm-svn: 360493
* [ARM] Move InstPrinter files to MCTargetDesc. NFCRichard Trieu2019-05-1112-36/+11
| | | | | | | | | For some targets, there is a circular dependency between InstPrinter and MCTargetDesc. Merging them together will fix this. For the other targets, the merging is to maintain consistency so all targets will have the same structure. llvm-svn: 360490
* [ARC] Move InstPrinter files to MCTargetDesc. NFCRichard Trieu2019-05-1110-31/+5
| | | | | | | | | For some targets, there is a circular dependency between InstPrinter and MCTargetDesc. Merging them together will fix this. For the other targets, the merging is to maintain consistency so all targets will have the same structure. llvm-svn: 360488
* [AMDGPU] Move InstPrinter files to MCTargetDesc. NFCRichard Trieu2019-05-1111-37/+11
| | | | | | | | | For some targets, there is a circular dependency between InstPrinter and MCTargetDesc. Merging them together will fix this. For the other targets, the merging is to maintain consistency so all targets will have the same structure. llvm-svn: 360487
* [AArch64] Move InstPrinter files to MCTargetDesc. NFCRichard Trieu2019-05-1010-39/+9
| | | | | | | | | For some targets, there is a circular dependency between InstPrinter and MCTargetDesc. Merging them together will fix this. For the other targets, the merging is to maintain consistency so all targets will have the same structure. llvm-svn: 360486
* [XCore] Move InstPrinter files to MCTargetDesc. NFCRichard Trieu2019-05-1010-34/+8
| | | | | | | | | For some targets, there is a circular dependency between InstPrinter and MCTargetDesc. Merging them together will fix this. For the other targets, the merging is to maintain consistency so all targets will have the same structure. llvm-svn: 360485
* [X86] Move InstPrinter files to MCTargetDesc. NFCRichard Trieu2019-05-1022-58/+33
| | | | | | | | | For some targets, there is a circular dependency between InstPrinter and MCTargetDesc. Merging them together will fix this. For the other targets, the merging is to maintain consistency so all targets will have the same structure. llvm-svn: 360484
* Revert [DAGCombiner] Avoid creating large tokenfactors in visitTokenFactorJordan Rupprecht2019-05-101-3/+2
| | | | | | This reverts r360171 (git commit a9d6c32eafc645c55b07eb50698c428e14c0bffd). A repro showing the asan/msan failures is forthcoming. llvm-svn: 360481
* Factor out redzone ABI checks [NFCI]Philip Reames2019-05-104-5/+18
| | | | | | | | | | As requested in D58632, cleanup our red zone detection logic in the X86 backend. The existing X86MachineFunctionInfo flag is used to track whether we *use* the redzone (via a particularly optimization?), but there's no common way to check whether the function *has* a red zone. I'd appreciate careful review of the uses being updated. I think they are NFC, but a careful eye from someone else would be appreciated. Differential Revision: https://reviews.llvm.org/D61799 llvm-svn: 360479
* [ORC] Make a narrowing-cast explicit to silence a compiler warning.Lang Hames2019-05-101-1/+1
| | | | llvm-svn: 360478
* [JITLink][MachO] Mark atoms in sections 'no-dead-strip' set live by default.Lang Hames2019-05-102-36/+66
| | | | | | | | If a MachO section has the no-dead-strip attribute set then its atoms should be preserved, regardless of whether they're public or referenced elsewhere in the object. llvm-svn: 360477
* [X86] Disable speculative load hardening for operations with an explicit RSP ↵Craig Topper2019-05-101-0/+8
| | | | | | | | | | | | | | base. After D58632, we can create idempotent atomic operations to the top of stack. This confused speculative load hardening because it thinks accesses should have virtual register base except for the cases it already excluded. This commit adds a new exclusion for this case. I'll try to reduce a test case for this, but this fix was verified to work by the reporter. This should avoid needing to revert D58632. llvm-svn: 360475
* [COFF] Fix .bss section size bug in obj2yaml / yaml2objReid Kleckner2019-05-101-0/+6
| | | | | | | | | We need to serialize SizeOfRawData through even when there is no data, as in a .bss section. Fixes PR41836 llvm-svn: 360473
* [LegalizeVectorOps] Remove calls to LegalizeOp on the return value from ↵Craig Topper2019-05-101-2/+2
| | | | | | | | | | ExpandLoad/ExpandStore. We already updated the LegalizedNodes map at the end of the Expand call. This would have marked the new node as being mapped to itself. So the LegalizeOp call will find that an immediately return. llvm-svn: 360472
* Skip over prefetchesMircea Trofin2019-05-101-0/+16
| | | | | | | | | | | | | | | | Summary: Skip over prefetches when assigning debug info to instructions with memory operands. This way, the debug info is stable after instrumenting a binary with prefetches, allowing for iterative profiling and instrumentation. Reviewers: davidxl Reviewed By: davidxl Subscribers: aprantl, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D61789 llvm-svn: 360471
* [SDAG] Recursively legalize both vector mulo resultsNikita Popov2019-05-101-3/+7
| | | | | | | | | | | | | | | | Split out from D61692 per RKSimon's suggestion. Vector op legalization will automatically recursively legalize the returned SDValue, but we need to take care of the other results ourselves. Otherwise it will end up getting legalized only during op legalization, by which point it might be too late (though I'm not aware of any specific cases right now). There are codegen differences because expansion occurs earlier now and we don't get a DAGCombiner run in between. Differential Revision: https://reviews.llvm.org/D61744 llvm-svn: 360470
* [ThinLTO] Auto-hide prevailing linkonce_odr only when all copies eligibleTeresa Johnson2019-05-1011-60/+117
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: We hit undefined references building with ThinLTO when one source file contained explicit instantiations of a template method (weak_odr) but there were also implicit instantiations in another file (linkonce_odr), and the latter was the prevailing copy. In this case the symbol was marked hidden when the prevailing linkonce_odr copy was promoted to weak_odr. It led to unsats when the resulting shared library was linked with other code that contained a reference (expecting to be resolved due to the explicit instantiation). Add a CanAutoHide flag to the GV summary to allow the thin link to identify when all copies are eligible for auto-hiding (because they were all originally linkonce_odr global unnamed addr), and only do the auto-hide in that case. Most of the changes here are due to plumbing the new flag through the bitcode and llvm assembly, and resulting test changes. I augmented the existing auto-hide test to check for this situation. Reviewers: pcc Subscribers: mehdi_amini, inglorion, eraman, dexonsmith, arphaman, dang, llvm-commits, steven_wu, wmi Tags: #llvm Differential Revision: https://reviews.llvm.org/D59709 llvm-svn: 360466
* [DAGCombiner] reduce code duplication; NFCSanjay Patel2019-05-101-10/+8
| | | | llvm-svn: 360462
* Add InstCombine::visitFNeg(...)Cameron McInally2019-05-102-0/+10
| | | | | | Differential Revision: https://reviews.llvm.org/D61784 llvm-svn: 360461
* DebugInfo: Only move types out of type units if they're named or type unitedDavid Blaikie2019-05-103-6/+15
| | | | | | | | | | | | | | | | | | Follow up to r359122, after a bug was reported in it - the original change too aggressively tried to move related types out of type units, which included unnamed types (like array types) which can't reasonably be declared-but-not-defined. A step beyond that is that some types in type units can be anonymous, if they are types with a name for linkage purposes (eg: "typedef struct { } x;"). So ensure those don't get turned into plain declarations (without signatures) because, lacking names, they can't be resolved to the definition. [Also include a fix for llvm-dwarfdump/libDebugInfoDWARF to pretty print types in type units] llvm-svn: 360458
* [SLP] Refactor VectorizableTree to use unique_ptr.Simon Pilgrim2019-05-101-48/+67
| | | | | | | | | | This patch fixes the TreeEntry dangling pointer issue caused by reallocations of VectorizableTree. Committed on behalf of @vporpo (Vasileios Porpodas) Differential Revision: https://reviews.llvm.org/D61706 llvm-svn: 360456
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