summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
...
* Revert "Emit DW_AT_object_pointer once, on the declaration, for each function."David Blaikie2014-04-304-18/+8
| | | | | | | | | | | | | | Breaks GDB buildbot (http://lab.llvm.org:8011/builders/clang-x86_64-ubuntu-gdb-75/builds/14517) GCC emits DW_AT_object_pointer /everywhere/ (declaration, abstract definition, inlined subroutine), but it looks like GCC relies on it being somewhere other than the declaration, at least. I'll experiment further & can hopefully still remove it from the inlined_subroutine. This reverts commit r207705. llvm-svn: 207719
* Prepare support of Itanium ABI on ARM as opposed to EHABI byJoerg Sonnenberger2014-04-302-15/+20
| | | | | | conditionally emitting .fnstart and friends only for EHABI. llvm-svn: 207718
* DebugInfo: Omit DW_AT_artificial on DW_TAG_formal_parameters in ↵David Blaikie2014-04-303-20/+32
| | | | | | | | | | | | DW_TAG_inlined_subroutines. They just don't need to be there - they're inherited from the abstract definition. In theory I would like them to be inherited from the declaration, but the DWARF standard doesn't quite say that... we can probably do it anyway but I'm less confident about that so I'll leave it for a separate commit. llvm-svn: 207717
* Restore condition incorrectly changed in r96289 to the older state.Joerg Sonnenberger2014-04-301-1/+1
| | | | llvm-svn: 207716
* Convert more loops to range-based equivalentsAlexey Samsonov2014-04-3013-130/+103
| | | | llvm-svn: 207714
* Patch for function cloning to inline all blocks whose address is takenGerolf Hoflehner2014-04-301-34/+106
| | | | | | | | | | | | | Not all address taken blocks get inlined. The reason is that a blocks new address is known only when it is cloned. But e.g. a branch instruction in a different block could need that address earlier while it gets cloned. The solution is to collect the set of all blocks that can potentially get inlined and compute a new block address up front. Then clone and cleanup. rdar://16427209 llvm-svn: 207713
* Provide a version of getSymbolOffset that returns false on error.Rafael Espindola2014-04-302-38/+49
| | | | | | | This simplifies ELFObjectWriter::SymbolValue a bit more. This new version will also be used in the COFF writer to fix pr19147. llvm-svn: 207711
* Slightly simplify code in DwarfDebug::beginFunctionAlexey Samsonov2014-04-301-7/+5
| | | | llvm-svn: 207710
* Move logic for calculating DBG_VALUE history map into separate file/class.Alexey Samsonov2014-04-305-124/+207
| | | | | | | | | | | | | | | | Summary: No functionality change. Test Plan: llvm regression test suite. Reviewers: dblaikie Reviewed By: dblaikie Subscribers: echristo, llvm-commits Differential Revision: http://reviews.llvm.org/D3573 llvm-svn: 207708
* Emit DW_AT_object_pointer once, on the declaration, for each function.David Blaikie2014-04-304-8/+18
| | | | | | | | | | | | | | | | This effectively reverts r164326, but adds some comments and justification and ensures we /don't/ emit the DW_AT_object_pointer on the (abstract and concrete) definitions. (while still preserving it on standalone definitions involving ObjC Blocks) This does increase the size of member function declarations from 7 to 11 bytes, unfortunately, but still seems like the Right Thing to do so that callers that see only the declaration still have the information about the object pointer. That said, I don't know what, if any, DWARF consumers don't have a heuristic to guess this in the case of normal C++ member functions - perhaps we can remove it entirely. llvm-svn: 207705
* [ARM64] Prevent bit extraction to be adjusted by following shiftWeiming Zhao2014-04-303-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | For pattern like ((x >> C1) & Mask) << C2, DAG combiner may convert it into (x >> (C1-C2)) & (Mask << C2), which makes pattern matching of ubfx more difficult. For example: Given %shr = lshr i64 %x, 4 %and = and i64 %shr, 15 %arrayidx = getelementptr inbounds [8 x [64 x i64]]* @arr, i64 0, %i64 2, i64 %and %0 = load i64* %arrayidx With current shift folding, it takes 3 instrs to compute base address: lsr x8, x0, #1 and x8, x8, #0x78 add x8, x9, x8 If using ubfx, it only needs 2 instrs: ubfx x8, x0, #4, #4 add x8, x9, x8, lsl #3 This fixes bug 19589 llvm-svn: 207702
* Fix the clang-cl self-host build by defining ~DwarfDebug out of lineReid Kleckner2014-04-302-0/+5
| | | | | | | | | | | | DwarfDebug.h has a SmallVector member containing a unique_ptr of an incomplete type. MSVC doesn't have key functions, so the vtable and dtor are emitted in AsmPrinter.cpp, where DwarfDebug's ctor is called. AsmPrinter.cpp include DwarfUnit.h and doesn't get a complete definition of DwarfTypeUnit. We could fix the problem by including DwarfUnit.h in DwarfDebug.h, but that would increase header bloat. Instead, define ~DwarfDebug out of line. llvm-svn: 207701
* Revert r207571 - Add slp vectorization to LTO passesYi Jiang2014-04-301-3/+0
| | | | llvm-svn: 207693
* [X86] Never hoist the shift value of a shift instruction.Michael Zolotukhin2014-04-301-3/+7
| | | | | | | | | | | There is no need to check if we want to hoist the immediate value of an shift instruction. Simply return TCC_Free right away. This change is like r206101, but for X86. rdar://problem/16190769 llvm-svn: 207692
* Convert several loops over MachineFunction basic blocks to range-based loopsAlexey Samsonov2014-04-307-58/+42
| | | | llvm-svn: 207683
* [IPO/MergeFunctions] changes so it doesn't try to bitcast a struct return ↵Carlo Kok2014-04-301-1/+16
| | | | | | type but instead recreates it with insert/extract value. llvm-svn: 207679
* IR: Conservatively verify inalloca argumentsDavid Majnemer2014-04-301-0/+10
| | | | | | | | | | | | Summary: Try to spot obvious mismatches with inalloca use. Reviewers: rnk Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D3572 llvm-svn: 207676
* Simplify ELFObjectWriter::SymbolValue.Rafael Espindola2014-04-301-22/+14
| | | | | | It now defers all offset computation to getSymbolOffset. llvm-svn: 207674
* [mips] Add instruction alias (negu).Matheus Almeida2014-04-301-0/+2
| | | | | | | | | | | | Summary: negu $reg is equivalent to negu $reg, $reg. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3510 llvm-svn: 207673
* [mips] Add instruction alias (sltu).Matheus Almeida2014-04-301-0/+2
| | | | | | | | | | | | | | Summary: The pattern sltu $r1, $r2, $imm is found in handwritten assembly which is just a shorthand version of sltui $r1, $r2, $imm. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3508 llvm-svn: 207671
* ELFObjectWriter: deduplicate suffices in strtabHans Wennborg2014-04-303-86/+84
| | | | | | | | | | | | | | | We already do this for shstrtab, so might as well do it for strtab. This extracts the string table building code into a separate class. The idea is to use it for other object formats too. I mostly wanted to do this for the general principle, but it does save a little bit on object file size. I tried this on a clang bootstrap and saved 0.54% on the sum of object file sizes (1.14 MB out of 212 MB for a release build). Differential Revision: http://reviews.llvm.org/D3533 llvm-svn: 207670
* ARM64: print fp immediates without using scientific notation.Tim Northover2014-04-301-6/+4
| | | | llvm-svn: 207669
* AArch64/ARM64: implement remaining TLS relocations (purely MC).Tim Northover2014-04-305-18/+34
| | | | llvm-svn: 207668
* AArch64/ARM64: add specific diagnostic for MRS/MSR and enable tests.Tim Northover2014-04-302-1/+9
| | | | llvm-svn: 207667
* AArch64/ARM64: accept and print floating-point immediate 0 as "#0.0"Tim Northover2014-04-302-19/+41
| | | | | | | | | | It's been decided that in the future, the floating-point immediate in instructions like "fcmeq v0.2s, v1.2s, #0.0" will be canonically "0.0", which has been implemented on AArch64 already but not ARM64. This fixes that issue. llvm-svn: 207666
* IR: Alloca clones should remember inalloca stateDavid Majnemer2014-04-301-3/+4
| | | | | | | | | Pretty straightforward, we weren't propagating whether or not an AllocaInst had 'inalloca' marked on it when it came time to clone it. The inliner exposed this bug. A reduced testcase is forthcoming. llvm-svn: 207665
* [mips] Add instruction alias (dsll and dsrl).Matheus Almeida2014-04-301-0/+4
| | | | | | | | | | | | | | Summary: The pattern dsll/dsrl $rd, $rt, $rs is found in handwritten assembly which is just a shorthand version of dsllv/dsrlv $rd, $rt, $rs. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3486 llvm-svn: 207664
* R600/SI: Use VALU instructions for copying i1 valuesTom Stellard2014-04-309-9/+149
| | | | | | | | | We can't use SALU instructions for this since they ignore the EXEC mask and are always executed. This fixes several OpenCV tests. llvm-svn: 207661
* R600/SI: Teach moveToVALU how to handle some SMRD instructionsTom Stellard2014-04-302-1/+49
| | | | llvm-svn: 207660
* [ARM64][fast-isel] Fast-isel doesn't know how to handle f128.Chad Rosier2014-04-301-1/+14
| | | | llvm-svn: 207659
* [mips] Add instruction alias (sll and srl).Matheus Almeida2014-04-301-0/+4
| | | | | | | | | | | | | | Summary: The pattern sll/srl $rd, $rt, $rs is found in handwritten assembly which is just a shorthand version of sllv/srlv $rd, $rt, $rs. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3483 llvm-svn: 207657
* [mips] Fix MipsLongBranch pass to work when the offset from the branch to theSasa Stankovic2014-04-308-33/+169
| | | | | | | | | | | | | | target cannot be determined accurately. This is the case for NaCl where the sandboxing instructions are added in MC layer, after the MipsLongBranch pass. It is also the case when the code has inline assembly. Instead of calculating offset in the MipsLongBranch pass, use %hi(sym1 - sym2) and %lo(sym1 - sym2) expressions that are resolved during the fixup. This patch also deletes microMIPS test file test/CodeGen/Mips/micromips-long-branch.ll and implements microMIPS CHECKs in a much simpler way in a file test/CodeGen/Mips/longbranch.ll, together with MIPS32 and MIPS64. llvm-svn: 207656
* R600: Remove unused function AMDGPUSubtarget::getDefaultSize()Tom Stellard2014-04-302-13/+0
| | | | llvm-svn: 207654
* [asan] Disable asm instrumentation on unsupported platforms.Evgeniy Stepanov2014-04-301-3/+6
| | | | | | | | | Only emit calls to compiler-rt asm routines on platforms where they are present (currently limited to linux i386/x86_64). Patch by Yuri Gorshenin. llvm-svn: 207651
* ARM64: print lsr instead of lsrv for variable shifts (etc)Tim Northover2014-04-301-13/+13
| | | | | | | The canonical syntax for shifts by a variable amount does not end with 'v', but that syntax should be supported as an alias (presumably for legacy reasons). llvm-svn: 207649
* ARM64: use 32-bit operations for uxtb & uxthTim Northover2014-04-301-3/+19
| | | | | | Testing will be enabled shortly with basic-a64-instructions.s llvm-svn: 207648
* AArch64/ARM64: allow smaller granule relocations on MOVZ/MOVNTim Northover2014-04-301-6/+6
| | | | | | Testing will be enabled shortly with basic-a64-instructions.s llvm-svn: 207647
* AArch64/ARM64: copy support for bCC instead of b.CC across.Tim Northover2014-04-301-0/+21
| | | | llvm-svn: 207646
* AArch64/ARM64: expunge CPSR from the sourcesTim Northover2014-04-3012-123/+125
| | | | | | | | | | | | AArch64 does not have a CPSR register in the same way that AArch32 does. Most of its compiler-relevant roles have been taken over by the more specific NZCV register (representing just the flags set by normal instructions). Its system control functions still remain, but are now under the pseudo-register referred to as "PSTATE". They're accessed via various MRS & MSR instructions described in the reference manual. llvm-svn: 207645
* AArch64/ARM64: use HS instead of CS & LO instead of CC.Tim Northover2014-04-304-20/+20
| | | | | | | | | On instructions using the NZCV register, a couple of conditions have dual representations: HS/CS and LO/CC (meaning unsigned-higher-or-same/carry-set and unsigned-lower/carry-clear). The first of these is more descriptive in most circumstances, so we should print it. llvm-svn: 207644
* Grammar fix.Rafael Espindola2014-04-301-1/+1
| | | | | | Thanks to Saleem Abdulrasool for noticing it. llvm-svn: 207643
* [mips][msa] Fix vector insertions where the index is variableDaniel Sanders2014-04-303-0/+172
| | | | | | | | | | | | | | | | | | | | | Summary: This isn't supported directly so we rotate the vector by the desired number of elements, insert to element zero, then rotate back. The i64 case generates rather poor code on MIPS32. There is an obvious optimisation to be made in future (do both insert.w's inside a shared rotate/unrotate sequence) but for now it's sufficient to select valid code instead of aborting. Depends on D3536 Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://reviews.llvm.org/D3537 llvm-svn: 207640
* ARM64: accept ELF-relocated load/store insts without a #.Tim Northover2014-04-301-0/+1
| | | | | | | E.g. we print "ldr x0, [x0, :lo12:symbol]" so we need to accept that syntax too. llvm-svn: 207639
* ARM64: remove duplication by templating InstPrinter methodsTim Northover2014-04-304-215/+65
| | | | | | No functional change, so no tests. llvm-svn: 207638
* [mips] Add support for .cpload.Matheus Almeida2014-04-303-0/+100
| | | | | | | | | | | | | | | | | | | | Summary: This directive is used for setting up $gp in the beginning of a function. It expands to three instructions if PIC is enabled: lui $gp, %hi(_gp_disp) addui $gp, $gp, %lo(_gp_disp) addu $gp, $gp, $reg _gp_disp is a special symbol that the linker sets to the distance between the lui instruction and the context pointer (_gp). Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3480 llvm-svn: 207637
* ARM64: use hex immediates for movz/movk instructionsTim Northover2014-04-301-0/+1
| | | | | | | | Since these are mostly used in "lsl #16", "lsl #32", "lsl #48" combinations to piece together an immediate in 16-bit chunks, hex is probably the most appropriate format. llvm-svn: 207635
* ARM64: hexify printing various immediate operandsTim Northover2014-04-303-0/+10
| | | | | | | | | | This is mostly aimed at the NEON logical operations and MOVI/MVNI (since they accept weird shifts which are more naturally understandable in hex notation). Also changes BRK/HINT etc, which is probably a neutral change, but easier than the alternative. llvm-svn: 207634
* ARM64: print canonical syntax for add/sub (imm) instructions.Tim Northover2014-04-301-3/+5
| | | | | | | | | | Since these instructions only accept a 12-bit immediate, possibly shifted left by 12, the canonical syntax used by the architecture reference manual is "#N {, lsl #12 }". We should accept an immediate that has already been shifted, (e.g. Also, print a comment giving the full addend since it can be helpful. llvm-svn: 207633
* [LCG] Add the really, *really* boring edge insertion case: adding anChandler Carruth2014-04-301-4/+19
| | | | | | | | | | edge entirely within an existing SCC. Shockingly, making the connected component more connected is ... a total snooze fest. =] Anyways, its wired up, and I even added a test case to make sure it pretty much sorta works. =D llvm-svn: 207631
* [ARM64] Simplify if condition.James Molloy2014-04-301-6/+2
| | | | | | | v2f32 and v4f32 were missed out of these conditions, so this is also a bugfix. llvm-svn: 207628
OpenPOWER on IntegriCloud