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* MIRParser: Avoid reading uninitialized memory on generic vregsJustin Bogner2017-11-171-0/+1
| | | | | | | | | | | | | | If a vreg's bank is specified in the registers block and one of its defs or uses also specifies the bank, we end up checking that the RegBank is equal to diagnose conflicting banks. The problem comes up for generic vregs, where we weren't fully initializing the VRegInfo when parsing the registers block, so we'd end up comparing a null pointer to uninitialized memory. This fixes a non-deterministic failure when round tripping through MIR with generic vregs. llvm-svn: 318543
* [ThinLTO] Remove too aggressive assertion in building function call graph.Volodymyr Sapsai2017-11-171-2/+3
| | | | | | | | | | | | | | | | The assertion was introduced in r317853 but there are cases when a call isn't handled either as direct or indirect. In this case we add a reference graph edge but not a call graph edge. Reviewers: tejohnson Reviewed By: tejohnson Subscribers: mehdi_amini, inglorion, eraman, hiraditya, efriedma, llvm-commits Differential Revision: https://reviews.llvm.org/D40056 llvm-svn: 318540
* Revert "[MC] Fix regression tests on Windows when git “core.autocrlf” is ↵Rafael Espindola2017-11-171-2/+0
| | | | | | | | | | set to true." This reverts commit r318528. MC/AsmParser/preserve-comments-crlf.s fails on linux. llvm-svn: 318533
* [AArch64] Adjust the cost model for Exynos M1 and M2Evandro Menezes2017-11-171-43/+78
| | | | | | Improve the accuracy of the model by specifying the proper number of uops. llvm-svn: 318531
* [MC] Fix regression tests on Windows when git “core.autocrlf” is set to ↵Zhen Cao2017-11-171-0/+2
| | | | | | | | true. Differential Revision: https://reviews.llvm.org/D39737 llvm-svn: 318528
* [AMDGPU][MC][GFX9][disassembler] Corrected decoding of op_sel_hi for v_mad_mix*Dmitry Preobrazhensky2017-11-175-26/+26
| | | | | | | | | | See bug 35148: https://bugs.llvm.org//show_bug.cgi?id=35148 Reviewers: tamazov, SamWot, arsenm Differential Revision: https://reviews.llvm.org/D39492 llvm-svn: 318526
* [Support][CachePruning] Fix regression in pruning intervalBen Dunbobbin2017-11-171-1/+1
| | | | | | | | | | | | | Fixed broken comparison. borked by: rL284966 (see: https://reviews.llvm.org/D25730). Differential Revision: https://reviews.llvm.org/D40119 This is a second attempt to commit this. The first attempt broke lld and gold tests that had been written against the incorrect behaivour. llvm-svn: 318524
* [ARM] Use dwarf exception handling on MinGWMartin Storsjo2017-11-172-3/+10
| | | | | | | | | | | | | | | Enabling and using dwarf exceptions seems like an easier path to take, than to make the COFF/ARM backend output EHABI directives. Previously, no EH model was enabled at all on this target. There's no point in setting UseIntegratedAssembler to false since GNU binutils doesn't support Windows on ARM, and since we don't need to support external assembler, we don't need to use register numbers in cfi directives. Differential Revision: https://reviews.llvm.org/D39532 llvm-svn: 318510
* [SelectionDAG] Allow custom vector widening through ReplaceNodeResults to ↵Craig Topper2017-11-171-2/+7
| | | | | | | | | | handle nodes with chain outputs. Previously we were assuming all results were vectors and calling SetWidenedVector, but if its a chain result we should just replace uses instead. This fixes an error found by expensive checks after r318368. llvm-svn: 318509
* [IRCE] Remove folding of two range checks into RANGE_CHECK_BOTHMax Kazantsev2017-11-171-28/+3
| | | | | | | | | | | | | The logic of replacing of a couple `RANGE_CHECK_LOWER + RANGE_CHECK_UPPER` into `RANGE_CHECK_BOTH` in fact duplicates the logic of range intersection which happens when we calculate safe iteration space. Effectively, the result of intersection of these ranges doesn't differ from the range of merged range check. We chose to remove duplicating logic in favor of code simplicity. Differential Revision: https://reviews.llvm.org/D39589 llvm-svn: 318508
* AMDGPU: Replace list of SMEM buffer opcodesMatt Arsenault2017-11-172-10/+14
| | | | llvm-svn: 318506
* AMDGPU: Fix breaking SMEM clausesMatt Arsenault2017-11-172-25/+45
| | | | | | | | This was completely ignoring subregisters, so was not very useful. Also only break them if xnack is actually enabled. llvm-svn: 318505
* [SelectionDAG] Consolidate (t|T)ransferDbgValues methods, NFC (reapply)Vedant Kumar2017-11-172-39/+32
| | | | | | | | | | | | | | | | | | TransferDbgValues (capital 'T') is wired into ReplaceAllUsesWith, and transferDbgValues (lowercase 't') is used elsewhere (e.g in Legalize). Both functions should be doing the exact same thing. This patch consolidates the logic into one place. This was reverted in r318455 because some newly introduced asserts, which I thought were NFC, were firing. I filed PR35338. For now I've weakened the asserts. Testing: check-llvm, check-clang, and a stage2 Rel+Deb build of clang Differential Revision: https://reviews.llvm.org/D40104 llvm-svn: 318498
* Fix a bunch more layering of CodeGen headers that are in TargetDavid Blaikie2017-11-17370-631/+631
| | | | | | | | All these headers already depend on CodeGen headers so moving them into CodeGen fixes the layering (since CodeGen depends on Target, not the other way around). llvm-svn: 318490
* Don't #include MemoryBuffer.h from Host.h.Zachary Turner2017-11-172-0/+2
| | | | | | | | | | It turns out this #include isn't used from Host.h anyway, but by having it it causes circular include dependencies. This issues only surfaced while I was working on a separate patch, so I'm submitting this first so that it's independent of the other, unrelated patch. llvm-svn: 318489
* [PredicateInfo] Add comment about why we require stable sortMandeep Singh Grang2017-11-171-0/+5
| | | | llvm-svn: 318487
* Current implementation of Value::replaceUsesExceptBlockAddr() uses UseListDmitry Mikulin2017-11-171-1/+9
| | | | | | | | | | | | | iterator to walk the list which keeps changing inside the loop. When the UseList contains several uses with the same user, we end processing the same user more than once, which leads to an assert. With this fix, unique users are saved and processed later to avoid processing duplicates. Differential Revision: https://reviews.llvm.org/D39864 llvm-svn: 318477
* [ARM] 't' asm constraint should accept i32Yi Kong2017-11-161-1/+1
| | | | | | | | | | | | | | | | | | | | 't' constraint normally only accepts f32 operands, but for VCVT the operands can be i32. LLVM is overly restrictive and rejects asm like: float foo() { float result; __asm__ __volatile__( "vcvt.f32.s32 %[result], %[arg1]\n" : [result]"=t"(result) : [arg1]"t"(0x01020304) ); return result; } Relax the value type for 't' constraint to either f32 or i32. Differential Revision: https://reviews.llvm.org/D40137 llvm-svn: 318472
* [X86] Add DAG combine to remove sext i32->i64 from gather/scatter instructions.Craig Topper2017-11-161-1/+22
| | | | | | | | | | Only do this pre-legalize in case we're using the sign extend to legalize for KNL. This recovers all of the tests that changed when I stopped SelectionDAGBuilder from deleting sign extends. There's more work that could be done here particularly to fix the i8->i64 test case that experienced split. llvm-svn: 318468
* [X86] Don't remove sign extend of gather/scatter indices during ↵Craig Topper2017-11-161-7/+0
| | | | | | | | | | | | | | SelectionDAGBuilder. The sign extend might be from an i16 or i8 type and was inserted by InstCombine to match the pointer width. X86 gather legalization isn't currently detecting this to reinsert a sign extend to make things legal. It's a bit weird for the SelectionDAGBuilder to do this kind of optimization in the first place. With this removed we can at least lean on InstCombine somewhat to ensure the index is i32 or i64. I'll work on trying to recover some of the test cases by removing sign extends in the backend when its safe to do so with an understanding of the current legalizer capabilities. This should fix PR30690. llvm-svn: 318466
* [Support] Support NetBSD PaX MPROTECT in sys::Memory.Lang Hames2017-11-162-203/+4
| | | | | | | | | Removes AllocateRWX, setWritable and setExecutable from sys::Memory and standardizes on allocateMappedMemory / protectMappedMemory. The allocateMappedMemory method is updated to request full permissions for memory blocks so that they can be marked executable later. llvm-svn: 318464
* Fix some undefined beahvior in FileMapping.Zachary Turner2017-11-161-2/+2
| | | | | | | This was broken when building a 32-bit native toolchain, as shifting a size_t right by 32 is UB when sizeof(size_t) == 8. llvm-svn: 318462
* Convert another use of createUniqueFile to TempFile::create.Rafael Espindola2017-11-161-0/+16
| | | | | | | This one requires a new small feature in TempFile: the ability to keep the temporary file with the temporary name. llvm-svn: 318458
* Revert "[SelectionDAG] Consolidate (t|T)ransferDbgValues methods, NFC."Vedant Kumar2017-11-162-30/+39
| | | | | | | | | This reverts commit r318448. It looks like some of the asserts need to be weakened. http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-autoconf/builds/16296 llvm-svn: 318455
* [RISCV] Fix 64-bit data layout mismatch between backend and target descriptionMandeep Singh Grang2017-11-161-1/+1
| | | | | | | | | | | | Reviewers: asb Reviewed By: asb Subscribers: rbar, johnrusso, simoncook, jordy.potman.lists, llvm-commits Differential Revision: https://reviews.llvm.org/D40145 llvm-svn: 318454
* [X86] Pre-truncate gather/scatter indices that have element sizes larger ↵Craig Topper2017-11-161-2/+19
| | | | | | | | | | than 64-bits before Legalize. The wider element type will normally cause legalize to try to split and scalarize the gather/scatter, but we can't handle that. Instead, truncate the index early so the gather/scatter node is insulated from the legalization. This really shouldn't happen in practice since InstCombine will normalize index types to the same size as pointers. llvm-svn: 318452
* [X86] DAGCombinerInfo is in TargetLowering not X86TargetLowering.Craig Topper2017-11-161-1/+1
| | | | llvm-svn: 318451
* [DAGCombiner] Use cast instead of an unchecked dyn_cast.Craig Topper2017-11-161-1/+1
| | | | llvm-svn: 318450
* [SelectionDAG] Consolidate (t|T)ransferDbgValues methods, NFC.Vedant Kumar2017-11-162-39/+30
| | | | | | | | | | | | TransferDbgValues (capital 'T') is wired into ReplaceAllUsesWith, and transferDbgValues (lowercase 't') is used elsewhere (e.g in Legalize). Both functions should be doing the exact same thing. This patch consolidates the logic into one place. Differential Revision: https://reviews.llvm.org/D40104 llvm-svn: 318448
* Fix my typo of PDB_TableTypeReid Kleckner2017-11-161-1/+1
| | | | llvm-svn: 318447
* Fix -Wreturn-type falling off the end of a function in new DIA codeReid Kleckner2017-11-161-0/+1
| | | | llvm-svn: 318444
* [arc] Fix ambiguous overloaded operator errorDaniel Sanders2017-11-161-1/+1
| | | | | | | | lib/Target/ARC/ARCISelLowering.cpp:490:22: error: use of overloaded operator '<<' is ambiguous (with operand types 'llvm::raw_ostream' and 'llvm::MVT::SimpleValueType') << RegVT.getSimpleVT().SimpleTy << "\n"); ^ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ llvm-svn: 318443
* bpf: print backward branch target properlyYonghong Song2017-11-164-2/+18
| | | | | | | | | | | | | | | | | | | | | | | | Currently, it prints the backward branch offset as unsigned value like below: 7: 7d 34 0b 00 00 00 00 00 if r4 s>= r3 goto 11 <LBB0_3> 8: b7 00 00 00 00 00 00 00 r0 = 0 LBB0_2: 9: 07 00 00 00 01 00 00 00 r0 += 1 ...... 17: bf 31 00 00 00 00 00 00 r1 = r3 18: 6d 32 f6 ff 00 00 00 00 if r2 s> r3 goto 65526 <LBB0_3+0x7FFB0> The correct print insn 18 should be: 18: 6d 32 f6 ff 00 00 00 00 if r2 s> r3 goto -10 <LBB0_2> To provide better clarity and be consistent with kernel verifier output, the insn 7 output is changed to the following with "+" added to non-negative branch offset: 7: 7d 34 0b 00 00 00 00 00 if r4 s>= r3 goto +11 <LBB0_3> Signed-off-by: Yonghong Song <yhs@fb.com> Acked-by: Alexei Starovoitov <ast@kernel.org> llvm-svn: 318442
* [arc] Update TargetInfo to include the new backend name argumentDaniel Sanders2017-11-161-1/+1
| | | | | | | Also update a comment about the usage of RegisterTarget() that didn't mention the new argument. llvm-svn: 318441
* Fix RISCV build after r318352Azharuddin Mohammed2017-11-161-2/+2
| | | | | | | | | | | | Reviewers: asb, apazos, mgrang Reviewed By: mgrang Subscribers: rbar, johnrusso, simoncook, jordy.potman.lists, llvm-commits Differential Revision: https://reviews.llvm.org/D40139 llvm-svn: 318437
* [PPC] Change i32 constant in store instruction to i64Guozhi Wei2017-11-161-1/+16
| | | | | | | | This patch changes all i32 constant in store instruction to i64 with truncation, to increase the chance that the referenced constant can be shared with other i64 constant. Differential Revision: https://reviews.llvm.org/D39352 llvm-svn: 318436
* Add ELF dynamic symbol support to yaml2obj/obj2yamlDave Lee2017-11-161-0/+1
| | | | | | | | | | | | | | | | | | Summary: This change introduces a `DynamicSymbols` field to the ELF specific YAML supported by `yaml2obj` and `obj2yaml`. This grouping of symbols provides a way to represent ELF dynamic symbols. The `DynamicSymbols` structure is identical to the existing `Symbols`. Reviewers: compnerd, jakehehrlich, silvas Reviewed By: silvas Subscribers: silvas, jakehehrlich, llvm-commits Differential Revision: https://reviews.llvm.org/D39582 llvm-svn: 318433
* Allow empty mappings for optional YAML inputDave Lee2017-11-161-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This change fixes a bug where `obj2yaml` can in some cases produce YAML that causes `yaml2obj` to error. The ELF YAML document structure has a `Sections` mapping, which contains three mappings, all of which are optional: `Local`, `Global`, and `Weak.` Any one of these can be missing, but if all three are missing, then `yaml2obj` errors. This change allows YAML input for cases like this one. I have tested this with check-llvm and check-lld, and all tests passed. This change is the result of test failures while working on D39582, which introduces a `DynamicSymbols` mapping, which will be empty at times. Reviewers: compnerd, jakehehrlich, silvas, kledzik, mehdi_amini, pcc Reviewed By: compnerd Subscribers: silvas, llvm-commits Differential Revision: https://reviews.llvm.org/D39908 llvm-svn: 318428
* [asan] Fix small X86_64 ShadowOffset for non-default shadow scaleWalter Lee2017-11-161-7/+9
| | | | | | | | | | The requirement is that shadow memory must be aligned to page boundaries (4k in this case). Use a closed form equation that always satisfies this requirement. Differential Revision: https://reviews.llvm.org/D39471 llvm-svn: 318421
* Revert "[Support][CachePruning] Fix regression in pruning interval"Rafael Espindola2017-11-161-1/+1
| | | | | | | | This reverts commit r318397. It broke tools/gold/X86/cache.ll. llvm-svn: 318419
* [FuzzMutate] Fix windows build after rL318407.Igor Laevsky2017-11-161-1/+1
| | | | | | Add correct library dependence. llvm-svn: 318409
* [FuzzMutate] NFC. Move parseModule and writeModule from llvm-isel-fuzzer ↵Igor Laevsky2017-11-161-0/+36
| | | | | | | | into FuzzMutate. This is to be able to reuse them in the llvm-opt-fuzzer. llvm-svn: 318407
* [InstCombine] include 'sub' in the list of narrow-able binopsSanjay Patel2017-11-161-10/+7
| | | | | | | | | | | | | | | | | | | | // trunc (binop X, C) --> binop (trunc X, C') // trunc (binop (ext X), Y) --> binop X, (trunc Y) I'm grouping sub with the other binops because that makes the code simpler and the transforms are valid: https://rise4fun.com/Alive/UeF ...so even though we don't expect a sub with constant Op1 or any of the other opcodes with constant Op0 due to canonicalization rules, we might as well handle those situations if non-canonical code somehow reaches this point (it should just make instcombine more efficient in reaching its end goal). This should solve the problem that later manifests in the vectorizers in PR35295: https://bugs.llvm.org/show_bug.cgi?id=35295 llvm-svn: 318404
* [DebugInfo/PDB] Adding getUndecoratedNameEx and IPDB interfaces for ↵Aaron Smith2017-11-168-0/+151
| | | | | | | | | | | IDiaEnumTables and IDiaTable. Initial changes to support debugging PE/COFF files with LLDB on Windows through DIA SDK. There is another set of changes required on the LLDB side before this does anything. Differential Revision: https://reviews.llvm.org/D39517 llvm-svn: 318403
* [SCEV] simplify loop. NFC.Javed Absar2017-11-161-2/+2
| | | | | | Change loop to range-based llvm-svn: 318401
* Test commit. Add a missing dash to the standard llvm file header; NFC.Aaron Smith2017-11-161-1/+1
| | | | llvm-svn: 318400
* [Support][CachePruning] Fix regression in pruning intervalBen Dunbobbin2017-11-161-1/+1
| | | | | | | | | Fixed broken comparison. borked by: rL284966 (see: https://reviews.llvm.org/D25730). Differential Revision: https://reviews.llvm.org/D40119 llvm-svn: 318397
* [asan] Fix size/alignment issues with non-default shadow scaleWalter Lee2017-11-161-2/+5
| | | | | | | | | | | | | | | Fix a couple places where the minimum alignment/size should be a function of the shadow granularity: - alignment of AllGlobals - the minimum left redzone size on the stack Added a test to verify that the metadata_array is properly aligned for shadow scale of 5, to be enabled when we add build support for testing shadow scale of 5. Differential Revision: https://reviews.llvm.org/D39470 llvm-svn: 318395
* Fix pointer EVT in SelectionDAGBuilder::visitAllocaYaxun Liu2017-11-161-9/+7
| | | | | | | | | | | SelectionDAGBuilder::visitAlloca assumes alloca address space is 0, which is incorrect for triple amdgcn---amdgiz and causes isel failure. This patch fixes that. Differential Revision: https://reviews.llvm.org/D40095 llvm-svn: 318392
* [DAGCombine] Enable more srl -> load combinesSam Parker2017-11-161-5/+16
| | | | | | | | | | | | Change the calculation for the desired ValueType for non-sign extending loads, as in those cases we don't care about the higher bits. This creates a smaller ExtVT and allows for such combinations as: (srl (zextload i16, [addr]), 8) -> (zextload i8, [addr + 1]) Differential Revision: https://reviews.llvm.org/D40034 llvm-svn: 318390
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