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| author | Craig Topper <craig.topper@intel.com> | 2017-11-16 20:23:17 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2017-11-16 20:23:17 +0000 |
| commit | 04be793cecd837599243bc9439357529d8bea2ae (patch) | |
| tree | ebb254c041c73885d60491c60ab06ef3b4c40ce9 /llvm/lib | |
| parent | b6b61dfb15294005e72aa966e5157be1d32b7adc (diff) | |
| download | bcm5719-llvm-04be793cecd837599243bc9439357529d8bea2ae.tar.gz bcm5719-llvm-04be793cecd837599243bc9439357529d8bea2ae.zip | |
[X86] DAGCombinerInfo is in TargetLowering not X86TargetLowering.
llvm-svn: 318451
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index a89920d5537..67420fe0ea3 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -36032,7 +36032,7 @@ static SDValue combineSBB(SDNode *N, SelectionDAG &DAG) { // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS static SDValue combineADC(SDNode *N, SelectionDAG &DAG, - X86TargetLowering::DAGCombinerInfo &DCI) { + TargetLowering::DAGCombinerInfo &DCI) { // If the LHS and RHS of the ADC node are zero, then it can't overflow and // the result is either zero or one (depending on the input carry bit). // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1. |
