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* [NewPM] Emit inliner NoDefinition missed optimization remarkTeresa Johnson2018-05-081-1/+18
| | | | | | | | | | | | Summary: Makes this consistent with the old PM. Reviewers: eraman Subscribers: mehdi_amini, llvm-commits Differential Revision: https://reviews.llvm.org/D46526 llvm-svn: 331709
* [WebAssembly] MC: Use existing MCSymbol.Index field rather than inventing ↵Sam Clegg2018-05-081-15/+11
| | | | | | | | | | | | | extra mapping MCSymbol has getIndex/setIndex which are implementation defined and on other platforms are used to store the symbol table index. It makes sense to use this rather than invent a new mapping. Differential Revision: https://reviews.llvm.org/D46555 llvm-svn: 331705
* [MC] ELFObjectWriter: Removing unneeded variable and castSam Clegg2018-05-071-5/+4
| | | | | | Differential Revision: https://reviews.llvm.org/D46289 llvm-svn: 331704
* Revert r330742: Let TableGen write output only if it changed, instead of ↵Chandler Carruth2018-05-071-16/+5
| | | | | | | | | | | | | | | | | | | | doing so in cmake. This change causes us to re-run tablegen for every single target on every single build. This is much, much worse than the problem being fixed AFAICT. On my system, it makes a clean rebuild of `llc` with nothing changed go from .5s to over 8s. On systems with less parallelism, slower file systems, or high process startup overhead this will be even more extreme. The only way I see this could be a win is in clean builds where we churn the filesystem. But I think incremental rebuild is more important, and so if we want to re-instate this, it needs to be done in a way that doesn't trigger constant re-runs of tablegen. llvm-svn: 331702
* [MachineVerifier][GlobalISel] Checking that generic instrs have LLTs on all ↵Roman Tereshin2018-05-072-6/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | vregs Every generic machine instruction must have generic virtual registers only, that is, have a low-level type attached to each operand. Previously MachineVerifier would catch a type missing on an operand only if the previous operand for the the same type index exists and have a type attached to it and it will report it as a type mismatch. This is incosistent behaviour and a misleading error message. This commit makes sure MachineVerifier explicitly checks that the types are there for every operand and if not provides a straightforward error message. Reviewers: qcolombet t.p.northover bogner ab Reviewed By: qcolombet Subscribers: rovka, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D46455 llvm-svn: 331694
* [MachineVerifier][GlobalISel] NFC, Improving MO printing and refactoring ↵Roman Tereshin2018-05-072-21/+28
| | | | | | | | | | | | | | | | | | | | visitMachineInstrBefore This is an NFC pre-commit for the following "Checking that generic instrs have LLTs on all vregs" commit. This overloads MachineOperand::print to make it possible to print LLTs with standalone machine operands. This also overloads MachineVerifier::print(...MachineOperand...) with an optional LLT using the newly introduced MachineOperand::print variant; no actual calls added. This also refactors MachineVerifier::visitMachineInstrBefore in the parts dealing with all generic instructions (checking Selected property, LLTs, and phys regs). llvm-svn: 331693
* AMDGPU/GlobalISel: Don't try to lower hull shadersTom Stellard2018-05-071-2/+3
| | | | | | | | | | | | Summary: The AMDGPU_HS calling convention is not supported yet. Reviewers: arsenm, nhaehnle Subscribers: kzhuravl, wdng, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D46149 llvm-svn: 331691
* [DAGCombiner] Masked merge: enhance handling of 'andn' with immediatesRoman Lebedev2018-05-071-4/+14
| | | | | | | | | | | | | | | | | | | | | Summary: Split off from D46031. The previous patch, D46493, completely disabled unfolding in case of immediates. But we can do better: {F6120274} {F6120277} https://rise4fun.com/Alive/xJS Reviewers: spatel, craig.topper Reviewed By: spatel Subscribers: andreadb, llvm-commits Differential Revision: https://reviews.llvm.org/D46494 llvm-svn: 331685
* [DagCombiner] Not all 'andn''s work with immediates.Roman Lebedev2018-05-073-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: Split off from D46031. In masked merge case, this degrades IPC by decreasing instruction count. {F6108777} The next patch should be able to recover and improve this. This also affects the transform @spatel have added in D27489 / rL289738, and the test coverage for X86 was missing. But after i have added it, and looked at the changes in MCA, i'm somewhat confused. {F6093591} {F6093592} {F6093593} I'd say this regression is an improvement, since `IPC` increased in that case? Reviewers: spatel, craig.topper Reviewed By: spatel Subscribers: andreadb, llvm-commits, spatel Differential Revision: https://reviews.llvm.org/D46493 llvm-svn: 331684
* Remove explicit setting of the CFI jumptable section name, it does not appearDmitry Mikulin2018-05-071-6/+0
| | | | | | | | | | to be needed: jump table sections are created with .cfi.jumptable suffix. With this change each jump table is placed in a separate section, which allows the linker to re-order them. Differential Revision: https://reviews.llvm.org/D46537 llvm-svn: 331680
* [X86] Split WriteFAdd/WriteFCmp/WriteFMul schedule classesSimon Pilgrim2018-05-0712-172/+229
| | | | | | | | Split to support single/double for scalar, XMM and YMM/ZMM instructions - removing InstrRW overrides for these instructions. Fixes Atom ADDSUBPD instruction and reclassifies VFPCLASS as WriteFCmp which is closer in behaviour. llvm-svn: 331672
* [SelectionDAG] Transfer DbgValues when casts are optimized in ↵Aaron Smith2018-05-071-2/+4
| | | | | | | | | | | | | | | | | | | | | SelectionDAG::getNode Summary: getNode optimizes (ext (trunc x)) to x and the dbgvalue node on trunc is lost. The fix calls transferDbgValues to add the dbgvalue to x. Add DebugInfo/AArch64/dbg-value-i16.ll Patch by Sejong Oh! Reviewers: aprantl, javed.absar, llvm-commits, vsk Reviewed By: aprantl, vsk Subscribers: kristof.beyls, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D46348 llvm-svn: 331665
* [WebAssembly] Ensure all .debug_XXX section has proper symbol namesSam Clegg2018-05-072-4/+11
| | | | | | | | | | | Updated wasm section symbols names to match section name, and ensure all referenced sections will have a symbol (per DWARF spec v3, Figure 43) Patch by Yury Delendik! Differential Revision: https://reviews.llvm.org/D46543 llvm-svn: 331664
* [X86][AVX2] Tag VPMOVSX/VPMOVZX ymm instructions as WriteShuffle256Simon Pilgrim2018-05-076-82/+21
| | | | | | | | These are more like cross-lane shuffles than regular shuffles - we already do this for AVX512 equivalents. Differential Revision: https://reviews.llvm.org/D46229 llvm-svn: 331659
* [Hexagon] Move clamping of extended operands directly to MC code emitterKrzysztof Parzyszek2018-05-075-46/+38
| | | | llvm-svn: 331653
* [X86][Znver1] Remove WriteFMul/WriteFRcp InstRW overrides/aliases.Simon Pilgrim2018-05-071-44/+3
| | | | | | Fixes x87 schedules to more closely match Agner - AMD doesn't tend to "special case" x87 instructions as much as Intel. llvm-svn: 331645
* [X86] Split WriteFDiv schedule classes to support single/double scalar, XMM ↵Simon Pilgrim2018-05-0712-453/+206
| | | | | | | | and YMM/ZMM instructions. This removes all InstrRW overrides for these instructions - some x87 overrides remain but most use default (and realistic) values. llvm-svn: 331643
* [AMDGPU][Waitcnt] Remove the old waitcnt passMark Searles2018-05-075-718/+15
| | | | | | | | | Remove the old waitcnt pass ( si-insert-waits ), which is no longer maintained and getting crufty Differential Revision: https://reviews.llvm.org/D46448 llvm-svn: 331641
* Add option -verify-cfiinstrs to run verifier in CFIInstrInserterPetar Jovanovic2018-05-071-5/+11
| | | | | | | | | Instead of enabling it for non NDEBUG builds, use -verify-cfiinstrs to run verifier in CFIInstrInserter. It defaults to false. Differential Revision: https://reviews.llvm.org/D46444 llvm-svn: 331635
* [AMDGPU] Don't force WQM for DS opTim Renouf2018-05-071-3/+1
| | | | | | | | | | | | | | | | | | | | | | Summary: Previously, all DS ops forced WQM in a pixel shader. That was a hack to allow for graphics frontends using ds_swizzle to implement explicit derivatives, on SI/CI at least where DPP is not available. But it forced WQM for _any_ DS op. With this commit, DS ops no longer force WQM. Both graphics frontends (Mesa and LLPC) need to change to issue an explicit llvm.amdgcn.wqm intrinsic call when calculating explicit derivatives. The required Mesa change is: "amd/common: use llvm.amdgcn.wqm for explicit derivatives". Subscribers: qcolombet, arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D46051 Change-Id: I9b745b626fa91bbd66456e6cf41ee07eeea42f81 llvm-svn: 331633
* [X86] Split WriteFRcp/WriteFRsqrt/WriteFSqrt schedule classesSimon Pilgrim2018-05-0713-603/+228
| | | | | | | | | | | | | WriteFRcp/WriteFRsqrt are split to support scalar, XMM and YMM/ZMM instructions. WriteFSqrt is split into single/double/long-double sizes and scalar, XMM, YMM and ZMM instructions. This removes all InstrRW overrides for these instructions. NOTE: There were a couple of typos in the Znver1 model - notably a 1cy throughput for SQRT that is highly unlikely and doesn't tally with Agner. NOTE: I had to add Agner's numbers for several targets for WriteFSqrt80. llvm-svn: 331629
* Skip unreachable blocks for CFIInstrInserter verifyPetar Jovanovic2018-05-071-3/+4
| | | | | | | Iterate only through reachable blocks. This finetunes r330706 and it resolves build issue reported by Craig Topper. llvm-svn: 331628
* [SystemZ] Bugfix for MVCLoop CC clobbering.Jonas Paulsson2018-05-071-1/+1
| | | | | | | | MVCLoop clobbers CC (since it emits a compare/branch), but this was not modelled. Review: Ulrich Weigand llvm-svn: 331627
* [ARM] Select result 1 from ConvertBooleanCarryToCarryFlag's result ↵Amaury Sechet2018-05-071-4/+6
| | | | | | | | automatically. NFC The old behavior return the value 0, which is error prone. llvm-svn: 331614
* [TargetLowering] Use StringRef::split instead of SplitString. NFCCraig Topper2018-05-071-2/+2
| | | | | | SplitString splits based on a list of delimeters, but we're only using one delimeter so we should use the simpler split. llvm-svn: 331613
* [X86] Fix copy/paste mistake in comment. NFCCraig Topper2018-05-071-1/+1
| | | | llvm-svn: 331611
* [NFC][DAGCombine] unfoldMaskedMerge(): rename two variablesRoman Lebedev2018-05-061-4/+4
| | | | | | | The current names can be confused with the A and B sides of the canonical masked merge pattern. llvm-svn: 331609
* [X86] Enable reciprocal estimates for v16f32 vectors by using ↵Craig Topper2018-05-061-6/+10
| | | | | | | | | | | | | | | | | | | VRCP14PS/VRSQRT14PS Summary: The legacy VRCPPS/VRSQRTPS instructions aren't available in 512-bit versions. The new increased precision versions are. So we can use those to implement v16f32 reciprocal estimates. For KNL CPUs we can probably use VRCP28PS/VRSQRT28PS and avoid the NR step altogether, but I leave that for a future patch. Reviewers: spatel Reviewed By: spatel Subscribers: RKSimon, llvm-commits, mehdi_amini Differential Revision: https://reviews.llvm.org/D46498 llvm-svn: 331606
* [globalisel] Update GlobalISel emitter to match new representation of ↵Daniel Sanders2018-05-052-4/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | extending loads Summary: Previously, a extending load was represented at (G_*EXT (G_LOAD x)). This had a few drawbacks: * G_LOAD had to be legal for all sizes you could extend from, even if registers didn't naturally hold those sizes. * All sizes you could extend from had to be allocatable just in case the extend went missing (e.g. by optimization). * At minimum, G_*EXT and G_TRUNC had to be legal for these sizes. As we improve optimization of extends and truncates, this legality requirement would spread without considerable care w.r.t when certain combines were permitted. * The SelectionDAG importer required some ugly and fragile pattern rewriting to translate patterns into this style. This patch changes the representation to: * (G_[SZ]EXTLOAD x) * (G_LOAD x) any-extends when MMO.getSize() * 8 < ResultTy.getSizeInBits() which resolves these issues by allowing targets to work entirely in their native register sizes, and by having a more direct translation from SelectionDAG patterns. Each extending load can be lowered by the legalizer into separate extends and loads, however a target that supports s1 will need the any-extending load to extend to at least s8 since LLVM does not represent memory accesses smaller than 8 bit. The legalizer can widenScalar G_LOAD into an any-extending load but sign/zero-extending loads need help from something else like a combiner pass. A follow-up patch that adds combiner helpers for for this will follow. The new representation requires that the MMO correctly reflect the memory access so this has been corrected in a couple tests. I've also moved the extending loads to their own tests since they are (mostly) separate opcodes now. Additionally, the re-write appears to have invalidated two tests from select-with-no-legality-check.mir since the matcher table no longer contains loads that result in s1's and they aren't legal in AArch64 anymore. Depends on D45540 Reviewers: ab, aditya_nandakumar, bogner, rtereshin, volkan, rovka, javed.absar Reviewed By: rtereshin Subscribers: javed.absar, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D45541 llvm-svn: 331601
* [MIRPraser] Improve error checking for typed immediate operandsHeejin Ahn2018-05-051-6/+13
| | | | | | | | | | | | | | Summary: This improves error checks for typed immediate operands introduced in D45948 (rL331586), and removes a code block copied by mistake. Reviewers: rtereshin Subscribers: dschuff, sbc100, jgravelle-google, llvm-commits Differential Revision: https://reviews.llvm.org/D46491 llvm-svn: 331600
* Simplify LLVM_ATTRIBUTE_USED call sites.Fangrui Song2018-05-053-15/+7
| | | | llvm-svn: 331599
* [DAGCombiner] Masked merge: don't touch "not" xor's.Roman Lebedev2018-05-051-0/+10
| | | | | | | | | | | | | | | | | | | | Summary: Split off form D46031. It seems we don't want to transform the pattern if the `xor`'s are actually `not`'s. In vector case, this breaks `andnpd` / `vandnps` patterns. That being said, we may want to re-visit this `not` handling, maybe in D46073. Reviewers: spatel, craig.topper, javed.absar Reviewed By: spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D46492 llvm-svn: 331595
* [LTO] Handle Task=-1 passed to addSaveTempsTeresa Johnson2018-05-051-3/+5
| | | | | | | | | | | | | | | | | | | Summary: This change is necessary for D46464, which will pass -1 as the Task ID for distributed backends, so that the save temps files don't end up with "4294967295" in their path. For distributed back ends, when -1 is passed, don't append any Task ID. An existing test (tools/clang/test/CodeGen/thinlto_backend.ll) will fail without this change after D46464. Reviewers: pcc Subscribers: mehdi_amini, inglorion, llvm-commits Differential Revision: https://reviews.llvm.org/D46488 llvm-svn: 331591
* [NFC][DagCombiner] unfoldMaskedMerge(): improve readability.Roman Lebedev2018-05-051-4/+4
| | | | llvm-svn: 331588
* [CaptureTracking] Handle capturing of launder.invariant.groupPiotr Padlewski2018-05-051-22/+23
| | | | | | | | | | | | | | | | | | Summary: launder.invariant.group has the same rules of capturing as bitcast, gep, etc - the original value is not captured if the returned pointer is not captured. With this patch, we mark 40% more functions as noalias when compiling with -fstrict-vtable-pointers; 1078 vs 1778 (39.37%) Reviewers: sanjoy, davide, nlewycky, majnemer, mehdi_amini Subscribers: JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D32673 llvm-svn: 331587
* [MIRParser] Allow register class names in the form of integer/scalarHeejin Ahn2018-05-053-29/+18
| | | | | | | | | | | | | | | | Summary: The current code cannot handle register class names like 'i32', which is a valid register class name in WebAssembly. This patch removes special handling for integer/scalar/pointer type parsing and treats them as normal identifiers. Reviewers: thegameg Subscribers: jfb, dschuff, sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D45948 llvm-svn: 331586
* Range-ify for loop; NFCGeorge Burgess IV2018-05-051-2/+1
| | | | llvm-svn: 331582
* Fix a bunch of places where operator-> was used directly on the return from ↵Craig Topper2018-05-0514-26/+24
| | | | | | | | | | dyn_cast. Inspired by r331508, I did a grep and found these. Mostly just change from dyn_cast to cast. Some cases also showed a dyn_cast result being converted to bool, so those I changed to isa. llvm-svn: 331577
* LowerTypeTests: Fix non-determinism in code that handles icall branch funnels.Peter Collingbourne2018-05-051-13/+26
| | | | | | | | | This was exposed by enabling expensive checks, which causes llvm::sort to sort randomly. Differential Revision: https://reviews.llvm.org/D45901 llvm-svn: 331573
* [LTO] Allow pass remarks with hotness to be set when emitting to stderrTeresa Johnson2018-05-041-2/+2
| | | | | | | | | | | | | | | | | | | | | Summary: Set setDiagnosticsHotnessRequested before the early exit check for a diagnostic output file, so that pass remarks with hotness works when emitting pass remarks to stderr (e.g. via -pass-remarks=.). Also fix the llvm-lto2 diagnistic handler so that it only calls exit(1) when the diagnistic is an error type. Otherwise the new test invocation of llvm-lto2 with -pass-remarks causes it to fail. The new code is consistent with the diagnostic handler elsewhere (e.g. on the LLVMContext). Reviewers: pcc, davide Subscribers: fhahn, mehdi_amini, llvm-commits, inglorion Differential Revision: https://reviews.llvm.org/D46387 llvm-svn: 331569
* Mapping SDNode flags to MachineInstr flagsMichael Berg2018-05-041-1/+26
| | | | | | | | | | | | | | Summary: Providing the glue to map SDNode fast math sub flags to MachineInstr fast math sub flags. Reviewers: spatel, arsenm, wristow Reviewed By: spatel Subscribers: wdng Differential Revision: https://reviews.llvm.org/D46447 llvm-svn: 331567
* AMDGPU/NFC: Update D16PreservesUnusedBits description based Tony Tye's commentsKonstantin Zhuravlyov2018-05-041-1/+3
| | | | llvm-svn: 331564
* [LICM] Compute a must execute property for the prefix of the header as we goPhilip Reames2018-05-041-3/+14
| | | | | | | | Computing this property within the existing walk ensures that the cost is linear with the size of the block. If we did this from within isGuaranteedToExecute, it would be quadratic without some very fancy caching. This allows us to reliably catch a hoistable instruction within a header which may throw at some point *after* our hoistable instruction. It doesn't do anything for non-header cases, but given how common single block loops are, this seems very worthwhile. llvm-svn: 331557
* AMDGPU/NFC: Fix formatting for 900, 902 ISA Version featuresKonstantin Zhuravlyov2018-05-041-4/+2
| | | | llvm-svn: 331553
* AMDGPU: Add D16 instructions preserve unused bits featureKonstantin Zhuravlyov2018-05-046-9/+27
| | | | | | | | | - Predicate D16 patterns on this new feature - Added this new feature to gfx900/2/4 Differential Revision: https://reviews.llvm.org/D46366 llvm-svn: 331551
* [MachineLICM] Debug intrinsics shouldn't affect hoist decisionsGeoff Berry2018-05-041-0/+4
| | | | | | | | | | | | | | | | Summary: When checking if an instruction stores to a given frame index, check that the instruction can write to memory before looking at the memory operands list to avoid e.g. DBG_VALUE instructions that reference a frame index preventing a load from that index from being hoisted. Reviewers: dblaikie, MatzeB, qcolombet, reames, javed.absar Subscribers: mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D46284 llvm-svn: 331549
* [ObjCARC] Account for catchswitch in bitcast insertionShoaib Meenai2018-05-041-4/+17
| | | | | | | | | | | | | A catchswitch is both a pad and a terminator, meaning it must be the only non-phi instruction in its basic block. When we're inserting a bitcast in the incoming basic block for a phi, if that incoming block is a catchswitch, we should go up the dominator tree to find a valid insertion point rather than attempting to insert before the catchswitch (which would result in invalid IR). Differential Revision: https://reviews.llvm.org/D46412 llvm-svn: 331548
* Fast Math Flag mapping into SDNodeMichael Berg2018-05-045-15/+18
| | | | | | | | | | | | | | Summary: Adding support for Fast flags in the SDNode to leverage fast math sub flag usage. Reviewers: spatel, arsenm, jbhateja, hfinkel, escha, qcolombet, echristo, wristow, javed.absar Reviewed By: spatel Subscribers: llvm-commits, rampitec, nhaehnle, tstellar, FarhanaAleen, nemanjai, javed.absar, jbhateja, hfinkel, wdng Differential Revision: https://reviews.llvm.org/D45710 llvm-svn: 331547
* [X86] Add WriteEMMS scheduler classSimon Pilgrim2018-05-0412-34/+15
| | | | | | Filled in the missing values from Btver2 SoG or Agner llvm-svn: 331546
* [X86] Finish splitting WriteVecShift and WriteVecIMul to remove InstRW ↵Simon Pilgrim2018-05-0411-103/+44
| | | | | | overrides. llvm-svn: 331543
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