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* [ARM] Mark VMOVDRR with the RegSequence property and implement the relatedQuentin Colombet2014-08-113-0/+46
| | | | | | | | | | | | | target hook. This patch teaches the compiler that: dX = VMOVDRR rY, rZ is the same as: dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1 <rdar://problem/12702965> llvm-svn: 215404
* Make these DebugLocEntry::Value comparison operators friend functionsAdrian Prantl2014-08-111-24/+34
| | | | | | as suggested by dblaikie in a comment on r215384. llvm-svn: 215403
* Add missing closing namespace comment.Jim Grosbach2014-08-111-1/+1
| | | | llvm-svn: 215402
* AArch64: Tidy up a few comments.Jim Grosbach2014-08-111-2/+2
| | | | | | Have the comments match the actual parameter names. Found via clang-tidy. llvm-svn: 215401
* InstCombine: Combine (add (and %a, %b) (or %a, %b)) to (add %a, %b)David Majnemer2014-08-111-1/+23
| | | | | | | | | | | | | | What follows bellow is a correctness proof of the transform using CVC3. $ < t.cvc A, B : BITVECTOR(32); QUERY BVPLUS(32, A & B, A | B) = BVPLUS(32, A, B); $ cvc3 < t.cvc Valid. llvm-svn: 215400
* R600/SI: Add a ComplexPattern for selecting MUBUF _OFFSET variantTom Stellard2014-08-114-155/+289
| | | | | | | This saves us from having to copy a 64-bit 0 value into VGPRs for BUFFER_* instruction which only have a 12-bit immediate offset. llvm-svn: 215399
* R600/SI: Add an _OFFEN variant MUBUF_STORE_* and use it for scratch writesTom Stellard2014-08-112-23/+34
| | | | llvm-svn: 215398
* R600/SI: Clear lds bit on MUBUF instructions used for private storesTom Stellard2014-08-111-0/+1
| | | | | | | | This bit was left uninitialized, which was causing some random failures of piglit tests. NOTE: This is a candidate for the 3.5 branch. llvm-svn: 215396
* Add isRegSequence property.Quentin Colombet2014-08-111-0/+25
| | | | | | | | | | | This patch adds a new property: isRegSequence and the related target hooks: TargetIntrInfo::getRegSequenceInputs and TargetInstrInfo::getRegSequenceLikeInputs to specify that a target specific instruction is a (kind of) REG_SEQUENCE. <rdar://problem/12702965> llvm-svn: 215394
* [AArch64] Fix registerAllocator assigns same register for base and wback inQuentin Colombet2014-08-111-7/+6
| | | | | | | | pre/post-index load and store. Patch by Steven Wu <stevenwu@apple.com> llvm-svn: 215390
* Debug info: Remove an obsolete constructor from DebugLocEntry.Adrian Prantl2014-08-111-2/+2
| | | | llvm-svn: 215387
* Debug info: Modify DebugLocEntry::addValue to take multiple values so itAdrian Prantl2014-08-112-8/+9
| | | | | | only has to sort/unique values once per batch. llvm-svn: 215386
* Debug info: Further simplify the implementation of buildLocationList byAdrian Prantl2014-08-111-6/+6
| | | | | | getting rid of the redundant DIVariable in the OpenRanges pair. llvm-svn: 215385
* Debug Info: Move the sorting and uniqueing of pieces from emitLocPieces()Adrian Prantl2014-08-112-18/+22
| | | | | | | into buildLocationList(). By keeping the list of Values sorted, DebugLocEntry::Merge can also merge multi-piece entries. llvm-svn: 215384
* Debug info: Refactor DebugLocEntry's Merge function to makeAdrian Prantl2014-08-112-14/+37
| | | | | | | | | | | | buildLocationLists easier to read. The previous implementation conflated the merging of individual pieces and the merging of entire DebugLocEntries. By splitting this functionality into two separate functions the intention of the code should be clearer. llvm-svn: 215383
* ARM: try harder to detect non-IT eligible instructionsSaleem Abdulrasool2014-08-111-7/+32
| | | | | | | | | | | | | | | | | | | For many Thumb-1 register register instructions, setting the CPSR is not permitted inside an IT block. We would not correctly flag those instructions. The previous change to identify this scenario was insufficient as it did not actually catch all the instances. The current list is formed by manual inspection of the ARMv6M ARM. The change to the Thumb2 IT block test is due to the fact that the new more stringent checking of the MIs results in the If Conversion pass being prevented from executing (since not all the instructions in the BB are predicable). This results in code gen changes. Thanks to Tim Northover for pointing out that the previous patch was insufficient and hinting that the use of the v6M ARM would be much easier to use than the v7 or v8! llvm-svn: 215382
* MC: Diagnose an unexpected token in COFF .section instead of assertingReid Kleckner2014-08-111-0/+4
| | | | | | | This can easily arise when trying to assemble and ELF style .section directive for a COFF object file. llvm-svn: 215373
* Fix typos:Sylvestre Ledru2014-08-116-6/+6
| | | | | | | * libaries => libraries * avaiable => available llvm-svn: 215366
* Fix use of uninitialized variable.Rafael Espindola2014-08-111-2/+6
| | | | | | | Fixes linking bitcode files that use the new style comdats for constructors with ones that don't. llvm-svn: 215364
* Use an early return. NFC.Rafael Espindola2014-08-111-8/+9
| | | | llvm-svn: 215363
* Revert r215359 - [mips] Implement .ent, .end, .frame, .mask and .fmask ↵Daniel Sanders2014-08-113-263/+22
| | | | | | | | assembler directives It seems to cause an lld test (elf/Mips/hilo16-3.test) to fail. Reverted while we investigate. llvm-svn: 215361
* [mips] Implement .ent, .end, .frame, .mask and .fmask assembler directivesDaniel Sanders2014-08-113-22/+263
| | | | | | | | Patch by Matheus Almeida and Toma Tabacu Differential Revision: http://reviews.llvm.org/D4179 llvm-svn: 215359
* PeepholeOptimizer: make parameter ref to SmallPtrSetImplHans Wennborg2014-08-111-2/+2
| | | | | | | This makes the function type independent of the in-line size of LocalMIs. llvm-svn: 215356
* Make this SmallVector size a power of two as suggested by ChandlerHans Wennborg2014-08-111-1/+1
| | | | llvm-svn: 215355
* AArch64: add support for dynamic-loader relocationsTim Northover2014-08-111-0/+11
| | | | | | | | | LLD needs them, and it's good to be able to print them properly when our object dumpers encounter them. Patch by Daniel Stewart. llvm-svn: 215352
* AVX-512: added a missing bitcast from v16f32 to v16i32Elena Demikhovsky2014-08-111-0/+1
| | | | llvm-svn: 215351
* ARM: __gnu_h2f_ieee and __gnu_f2h_ieee always use the soft-float calling ↵Oliver Stannard2014-08-111-0/+13
| | | | | | | | | | | | convention By default, LLVM uses the "C" calling convention for all runtime library functions. The half-precision FP conversion functions use the soft-float calling convention, and are needed for some targets which use the hard-float convention by default, so must have their calling convention explicitly set. llvm-svn: 215348
* In Machine CSE pass, the source register of a COPY machine instruction canJiangning Liu2014-08-111-11/+19
| | | | | | | | be propagated to all its users, and this propagation could increase the probability of finding common subexpressions. If the COPY has only one user, the COPY itself can be removed. llvm-svn: 215344
* In LVI(Lazy Value Info), originally value on a BB can only be caculated once,Jiangning Liu2014-08-111-2/+17
| | | | | | | | | and the lattice will be updated to be a state other than "undefined". This limiation could miss some opportunities of lowering "overdefined" to be an even accurate value. So this patch ask the algorithm to try to lower the lattice value again even if the value has been lowered to be "overdefined". llvm-svn: 215343
* Re-commit "Increase the size of this SmallVector in PeepholeOptimizer." ↵Hans Wennborg2014-08-111-3/+3
| | | | | | | | | (r215340) This time, also update the function that receives a reference to the SmallPtrSet as a parameter. llvm-svn: 215342
* Revert "Increase the size of this SmallVector in PeepholeOptimizer." (r215340)Hans Wennborg2014-08-111-1/+1
| | | | | | | | | | | | | That broke the build: /data/buildslave/clang-amd64-freebsd/src-llvm/lib/CodeGen/PeepholeOptimizer.cpp:729:46: error: non-const lvalue reference to type 'SmallPtrSet<[...], 8>' cannot bind to a value of unrelated type 'SmallPtrSet<[...], 16>' Changed |= optimizeExtInstr(MI, MBB, LocalMIs); ^~~~~~~~ /data/buildslave/clang-amd64-freebsd/src-llvm/lib/CodeGen/PeepholeOptimizer.cpp:265:49: note: passing argument to parameter 'LocalMIs' here SmallPtrSet<MachineInstr*, 8> &LocalMIs) { ^ llvm-svn: 215341
* Increase the size of this SmallVector in PeepholeOptimizer.Hans Wennborg2014-08-111-1/+1
| | | | | | During a Clang build, the median size of this was 9 llvm-svn: 215340
* SubTargetFeature.cpp: it seems the size of this SmallVector should be 3Hans Wennborg2014-08-111-1/+1
| | | | | | because some subtarget feature strings have three components. llvm-svn: 215339
* Increase the size of SpillPlacement::BlockFrequencies.Hans Wennborg2014-08-111-2/+2
| | | | | | This SmallVector's median size during a Clang build was 7. llvm-svn: 215338
* Increase the size of these SmallVectors in X86ISelLowering.cpp.Hans Wennborg2014-08-111-3/+3
| | | | | | In a Clang bootstrap, their sizes were always 12, 16 and 16, respectively. llvm-svn: 215336
* Increase the size of this SmallVector in CloneNodeWithValues.Hans Wennborg2014-08-111-1/+1
| | | | | | In a Clang bootstrap, the size of this vector was always 6. llvm-svn: 215335
* Increase the size of DwarfAccelTable::TableHeaderData::Atoms.Hans Wennborg2014-08-111-1/+1
| | | | | | During a Clang bootstrap, it seems this SmallVector always contains 3 elements. llvm-svn: 215334
* Add support for scalarizing cttz_zero_undefPetar Jovanovic2014-08-101-0/+1
| | | | | | | | | Follow up to r214266. Add missing case in ScalarizeVectorResult() for cttz_zero_undef. Differential Revision: http://reviews.llvm.org/D4813 llvm-svn: 215330
* ARM: correct isPredicable for MULS in ThHUMB modeSaleem Abdulrasool2014-08-101-0/+14
| | | | | | | | | | | | | | | | | | The ARM ARM states that CPSR may not be updated by a MUL in thumb mode. Due to an ordering of Thumb 2 Size Reduction and If Conversion, we would end up generating a THUMB MULS inside an IT block. The If Conversion pass uses the TTI isPredicable method to ensure that it can transform a Basic Block. However, because we only check for IT handling on Thumb2 functions, we may miss some cases. Even then, it only validates that the CPSR is not *live* rather than it is not accessed. This corrects the handling for that particular case since the same restriction does not hold on the vast majority of the instructions. This does prevent the IfConversion optimization from kicking in in certain cases, but generating correct code is more valuable. Addresses PR20555. llvm-svn: 215328
* @l and friends adjust their value depending the context used in.Joerg Sonnenberger2014-08-104-36/+142
| | | | | | | For ori, they are unsigned, for addi, signed. Create a new target expression type to handle this and evaluate Fixups accordingly. llvm-svn: 215315
* Fix tabs.Joerg Sonnenberger2014-08-101-4/+4
| | | | llvm-svn: 215311
* If available, pass down the Fixup object to EvaluateAsRelocatable.Joerg Sonnenberger2014-08-1015-46/+61
| | | | | | | At least on PowerPC, the interpretation of certain modifiers depends on the context they appear in. llvm-svn: 215310
* ADT: remove MinGW32 and Cygwin OSType enumSaleem Abdulrasool2014-08-091-9/+13
| | | | | | | | | | | Remove the MinGW32 and Cygwin types from the OSType enumeration. These values are represented via environments of Windows. It is a source of confusion and needlessly clutters the code. The cost of doing this is that we must sink the check for them into the normalization code path along with the spelling. Addresses PR20592. llvm-svn: 215303
* fixed typosSanjay Patel2014-08-091-2/+2
| | | | llvm-svn: 215299
* Resolving some type truncation warnings in MSVC (enum to bool in this case). ↵Aaron Ballman2014-08-091-3/+3
| | | | | | No functional changes intended. llvm-svn: 215293
* MC: remove duplicated codeSaleem Abdulrasool2014-08-091-14/+2
| | | | | | | | This removes the duplicate definition of GetXDataSection. This function is available as a static method and is identical to the previous implementation. This just cleans up the unnecessary duplication. llvm-svn: 215289
* MC: cleanup includesSaleem Abdulrasool2014-08-091-1/+0
| | | | | | Cleanup Win64EH header inclusion. NFC. llvm-svn: 215288
* CodeGen: switch to a range based for loopSaleem Abdulrasool2014-08-091-3/+4
| | | | | | Use a range based for loop instead of manual iteration. NFC. llvm-svn: 215287
* Allow the third argument for the subi family to be an expression.Joerg Sonnenberger2014-08-091-8/+27
| | | | llvm-svn: 215286
* Use the full form of dccci and iccci from the early PPC 405 documents,Joerg Sonnenberger2014-08-091-15/+9
| | | | | | | since the operands are actually used on those cores. Provide aliases for the only documented case in the newer Power ISA speec. llvm-svn: 215282
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