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* [llvm-dwarfdump] - Dump the older versions of .eh_frame/.debug_frame correctly.George Rimar2018-12-041-1/+2
| | | | | | | | | | | | | | | | | | | | | | The issue is the following. DWARF 2 used version 1 for .debug_frame. (Appendix G, p. 416 http://dwarfstd.org/doc/DWARF5.pdf) lib/MC now always sets version 1 for .eh_frame (and sets 1-4 versions for .debug_frame correctly): https://github.com/llvm-mirror/llvm/blob/master/lib/MC/MCDwarf.cpp#L1530 https://github.com/llvm-mirror/llvm/blob/master/lib/MC/MCDwarf.cpp#L1562 https://github.com/llvm-mirror/llvm/blob/master/lib/MC/MCDwarf.cpp#L1602 In version 1, return_address_register was defined as ubyte, while other versions switched to uleb128. (p 62, http://www.dwarfstd.org/doc/dwarf-2.0.0.pdf) Patch teaches llvm-dwarfdump about this difference. Differential revision: https://reviews.llvm.org/D54860 llvm-svn: 348242
* [X86] Remove custom DAG combine for ↵Craig Topper2018-12-041-45/+0
| | | | | | | | SIGN_EXTEND_VECTOR_INREG/ZERO_EXTEND_VECTOR_INREG. We only needed this because it provided really aggressive constant folding even through constant pool entries created from build_vectors. The main case was for vXi8 MULH legalization which was happening as part of legalize DAG instead of as part of legalize vector ops. Now its part of vector op legalization and we've added special handling for build vectors of all constants there. This has removed the need for this code on the list tests we have. llvm-svn: 348237
* Reverting r348215Ranjeet Singh2018-12-041-3/+4
| | | | | | Causing failures on ubsan buildbot boxes. llvm-svn: 348230
* [ExecutionEngine] Change NotifyObjectEmitted/NotifyObjectFreed API.Lang Hames2018-12-047-61/+66
| | | | | | | | | | | | | This patch renames both methods (NotifyObjectEmitted -> notifyObjectLoaded, and NotifyObjectFreed -> notifyObjectFreed), adds an abstract "ObjectKey" (uint64_t) parameter to notifyObjectLoaded, and replaces the ObjectFile parameter for notifyObjectFreed with an ObjectKey. Using an ObjectKey to track identify events, rather than a reference to the ObjectFile, allows us to free the ObjectFile after notifyObjectLoaded is called, saving memory. https://reviews.llvm.org/D53773 llvm-svn: 348223
* [ARM64][Windows] Fix local stack size for funcletsSanjin Sijaric2018-12-041-3/+8
| | | | | | | | | | | The comment was misplaced, and the code didn't do what the comment indicated, namely ignoring the varargs portion when computing the local stack size of a funclet in emitEpilogue. This results in incorrect offset computations within funclets that are contained in vararg functions. Differential Revision: https://reviews.llvm.org/D55096 llvm-svn: 348222
* [asan] Reduce binary size by using unnamed private aliasesVitaly Buka2018-12-041-3/+3
| | | | | | | | | | | | | | | Summary: --asan-use-private-alias increases binary sizes by 10% or more. Most of this space was long names of aliases and new symbols. These symbols are not needed for the ODC check at all. Reviewers: eugenis Subscribers: hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D55146 llvm-svn: 348221
* [MachineOutliner] Move stack instr check logic to getOutliningCandidateInfoJessica Paquette2018-12-041-96/+72
| | | | | | | | | | | | | | | | This moves the stack check logic into a lambda within getOutliningCandidateInfo. This allows us to be less conservative with stack checks. Whether or not a stack instruction is safe to outline is dependent on the frame variant and call variant of the outlined function; only in cases where we modify the stack can these be unsafe. So, if we move that logic later, when we're looking at an individual candidate, we can make better decisions here. This gives some code size savings as a result. llvm-svn: 348220
* [MachineOutliner][AArch64][NFC] Add early exit to candidate discarding logicJessica Paquette2018-12-041-0/+6
| | | | | | | | If we dropped too many candidates to be beneficial when dropping candidates that modify the stack, there's no reason to check for other cost model qualities. llvm-svn: 348219
* [ThinLTO] Look through aliases when computing hash keysGeorge Burgess IV2018-12-041-2/+8
| | | | | | | | | | | Without this, we don't consider types used by aliasees in our cache key. This caused issues when using the same cache for thin-linking the same TU with different sets of virtual call candidates for a virtual call inside of a constructor. That's sort of a mouthful. :) Differential Revision: https://reviews.llvm.org/D55060 llvm-svn: 348216
* [IR] Don't assume all functions are 4 byte alignedRanjeet Singh2018-12-041-4/+3
| | | | | | | | | | | In some cases different alignments for function might be used to save space e.g. thumb mode with -Oz will try to use 2 byte function alignment. Similar patch that fixed this in other areas exists here https://reviews.llvm.org/D46110 Differential Revision: https://reviews.llvm.org/D55115 llvm-svn: 348215
* [Hexagon] Switch to auto-generated intrinsic definitions and patternsKrzysztof Parzyszek2018-12-033-1233/+3613
| | | | llvm-svn: 348206
* [CodeExtractor] Split PHI nodes with incoming values from outlined region ↵Vedant Kumar2018-12-031-49/+90
| | | | | | | | | | | | | | | | | (PR39433) If a PHI node out of extracted region has multiple incoming values from it, split this PHI on two parts. First PHI has incomings only from region and extracts with it (they are placed to the separate basic block that added to the list of outlined), and incoming values in original PHI are replaced by first PHI. Similar solution is already used in CodeExtractor for PHIs in entry block (severSplitPHINodes method). It covers PR39433 bug. Patch by Sergei Kachkov! Differential Revision: https://reviews.llvm.org/D55018 llvm-svn: 348205
* Adapt gcov to changes in CFE.Adrian Prantl2018-12-031-7/+15
| | | | | | | | | | | | The clang frontend no longer emits the current working directory for DIFiles containing an absolute path in the filename: and will move the common prefix between current working directory and the file into the directory: component. This fixes the GCOV tests in compiler-rt that were broken by the Clang change. llvm-svn: 348203
* [Hexagon] Extract operand decoders into a separate file, NFCKrzysztof Parzyszek2018-12-032-56/+74
| | | | | | | These decoders are automatically generated. Keeping them separated makes updating architectures easier. llvm-svn: 348196
* [DAGCombiner] narrow truncated vector binops when legalSanjay Patel2018-12-032-7/+13
| | | | | | | | | | | | | | | | This is the smallest vector enhancement I could find to D54640. Here, we're allowing narrowing to only legal vector ops because we'll see regressions without that. All of the test diffs are wins from what I can tell. With AVX/AVX512, we can shrink ymm/zmm ops to xmm. x86 vector multiplies are the problem case that we're avoiding due to the patchwork ISA, and it's not clear to me if we can dance around those regressions using TLI hooks or if we need preliminary patches to plug those holes. Differential Revision: https://reviews.llvm.org/D55126 llvm-svn: 348195
* [mips] Fix TestDWARF32Version5Addr8AllForms test failure on MIPS hostsSimon Atanasyan2018-12-035-10/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | The `DIEExpr` is used in debug information entries for either TLS variables or call sites. For now the last case is unsupported for targets with delay slots, for MIPS in particular. The `DIEExpr::EmitValue` method calls a virtual `EmitDebugThreadLocal` routine which, in case of MIPS, always emits either `.dtprelword` or `.dtpreldword` directives. That is okay for "main" code, but in unit tests `DIEExpr` instances can be created not for TLS variables only even on MIPS hosts. That is a reason of the `TestDWARF32Version5Addr8AllForms` failure because handling of the `R_MIPS_TLS_DTPREL` relocation writes incorrect value into dwarf structures. And anyway unconditional emitting of `.dtprelword` directives will be incorrect when/if debug information entries for call sites become supported on MIPS. The patch solves the problem by wrapping expression created in the `MipsTargetObjectFile::getDebugThreadLocalSymbol` method in to the `MipsMCExpr` expression with a new `MEK_DTPREL` tag. This tag is recognized in the `MipsAsmPrinter::EmitDebugThreadLocal` method and `.dtprelword` directives created in this case only. In other cases the expression saved as a regular data. Differential Revision: http://reviews.llvm.org/D54937 llvm-svn: 348194
* [Hexagon] Remove unused encodings, NFCKrzysztof Parzyszek2018-12-031-741/+114
| | | | llvm-svn: 348193
* [InstCombine] fix undef propagation bug with shuffle+binopSanjay Patel2018-12-031-0/+16
| | | | | | | | | | | | | | When we have a shuffle that extends a source vector with undefs and then do some binop on that, we must make sure that the extra elements remain undef with that binop if we reverse the order of the binop and shuffle. 'or' is probably the easiest example to show the bug because 'or C, undef --> -1' (not undef). But there are other opcode/constant combinations where this is true as shown by the 'shl' test. llvm-svn: 348191
* [WebAssembly] Enforce assembler emits to streamer in order.Wouter van Oortmerssen2018-12-031-0/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: The assembler processes directives and instructions in whatever order they are in the file, then directly emits them to the streamer. This could cause badly written (or generated) .s files to produce incorrect binaries. It now has state that tracks what it has most recently seen, to enforce they are emitted in a given order that always produces correct wasm binaries. Also added a new test that compares obj2yaml output from llc (the backend) to that going via .s and the assembler to ensure both paths generate the same binaries. The features this test covers could be extended. Passes all wasm Lit tests. Fixes: https://bugs.llvm.org/show_bug.cgi?id=39557 Reviewers: sbc100, dschuff, aheejin Subscribers: jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D55149 llvm-svn: 348185
* [Hexagon] Update timing classesKrzysztof Parzyszek2018-12-035-5770/+5651
| | | | llvm-svn: 348183
* [InstCombine] foldICmpWithLowBitMaskedVal(): disable 2 faulty folds.Roman Lebedev2018-12-031-0/+4
| | | | | | | | | | | These two folds are invalid for this non-constant pattern when the mask ends up being all-ones: https://rise4fun.com/Alive/9au https://rise4fun.com/Alive/UcQM Fixes https://bugs.llvm.org/show_bug.cgi?id=39861 llvm-svn: 348181
* [TextAPI] Remove a superfluous semicolon, fixing GCC warnings. NFC.Martin Storsjo2018-12-031-1/+1
| | | | llvm-svn: 348179
* [COFF] Remove an outdated/incorrect comment. NFC.Martin Storsjo2018-12-031-4/+0
| | | | | | | | | | | | Making the section writable doesn't affect how windows does base relocs in case a DLL can't be loaded at the intended base address. This comment dates back to SVN r79346. Differential Revision: llvm-svn: 348178
* [COFF] Don't mark mingw .eh_frame sections writableMartin Storsjo2018-12-031-4/+4
| | | | | | | | | | | | | | This improves compatibility with GCC produced object files, where the .eh_frame sections are read only. With mixed flags for the involved .eh_frame sections, LLD creates two separate .eh_frame sections in the output binary, one for each flag combination, while ld.bfd probably merges them. The previous setup of flags can be traced back to SVN r79346. Differential Revision: https://reviews.llvm.org/D55209 llvm-svn: 348177
* [InstCombine] rearrange shuffle+binop fold; NFCSanjay Patel2018-12-031-8/+9
| | | | | | | | This code has a bug dealing with undefs, so we need to add another escape hatch, so doing some cleanup ahead of that. llvm-svn: 348175
* [Hexagon] Change instruction type field in TSFlags to 7 bitsKrzysztof Parzyszek2018-12-035-182/+177
| | | | llvm-svn: 348171
* [llvm-tapi] initial commit, supports ELF text stubsArmando Montanez2018-12-036-0/+236
| | | | | | | | | | | | | | | | | | | http://lists.llvm.org/pipermail/llvm-dev/2018-September/126472.html TextAPI is a library and accompanying tool that allows conversion between binary shared object stubs and textual counterparts. The motivations and uses cases for this are explained thoroughly in the llvm-dev proposal [1]. This initial commit proposes a potential structure for the TAPI library, also including support for reading/writing text-based ELF stubs (.tbe) in addition to preliminary support for reading binary ELF files. The goal for this patch is to ensure the project architecture appropriately welcomes integration of Mach-O stubbing from Apple's TAPI [2]. Added: - TextAPI library - .tbe read support - .tbe write (to raw_ostream) support [1] http://lists.llvm.org/pipermail/llvm-dev/2018-September/126472.html [2] https://github.com/ributzka/tapi Differential Revision: https://reviews.llvm.org/D53051 llvm-svn: 348170
* [MachineOutliner] Drop candidates that require fixups if it's beneficialJessica Paquette2018-12-031-5/+24
| | | | | | | | | | | | | | | | | | | | | | | If it's a bigger code size win to drop candidates that require stack fixups than to demote every candidate to that variant, the outliner should do that. This happens if the number of bytes taken by calls to functions that don't require fixups, plus the number of bytes that'd be left is less than the number of bytes that it'd take to emit a save + restore for all candidates. Also add tests for each possible new behaviour. - machine-outliner-compatible-candidates shows that when we have candidates that don't use the stack, we can use the default call variant along with the no save/regsave variant. - machine-outliner-all-stack shows that when it's better to fix up the stack, we still will demote all candidates to that case - machine-outliner-drop-stack shows that we can discard candidates that require stack fixups when it would be beneficial to do so. llvm-svn: 348168
* [Hexagon] Add HasV5 predicate for compatibility with auto-generated filesKrzysztof Parzyszek2018-12-031-6/+6
| | | | llvm-svn: 348167
* Fix issue with Tpi Stream hash map.Zachary Turner2018-12-031-0/+6
| | | | | | | | Part of the patch to not build the hash map eagerly was omitted due to a merge conflict. Add it back, which should fix the failing tests. llvm-svn: 348166
* [Hexagon] Remove unused operand definitions, NFCKrzysztof Parzyszek2018-12-031-8/+1
| | | | llvm-svn: 348163
* [Hexagon] Some formatting changes, NFCKrzysztof Parzyszek2018-12-032-5/+3
| | | | llvm-svn: 348162
* Don't build the Tpi Hash map by default.Zachary Turner2018-12-031-3/+0
| | | | | | | This is very slow and should be done for specific cases where lookups will need to happen. llvm-svn: 348160
* [X86] Teach LowerMUL/LowerMULH for vXi8 to unpack constant RHS.Craig Topper2018-12-031-42/+75
| | | | | | | | | | | | | | | | | | | Summary: We need to unpackl and unpackh the operands to use two vXi16 multiplies. Previously it looks like the low unpack would get constant folded at least in the 128-bit case after shuffle lowering turned the unpackl into ZERO_EXTEND_VECTOR_INREG and X86 custom DAG combined it. The same doesn't happen for the high half. So we'd load a constant and then shuffle it. But the low half would just be loaded and used by the multiply directly. After this patch we now end up with a constant pool entry for the low and high unpacks separately with no shuffle operations. This is a step towards removing custom constant folding for ZERO_EXTEND_VECTOR_INREG/SIGN_EXTEND_VECTOR_INREG in the X86 backend. Reviewers: RKSimon, spatel Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D55165 llvm-svn: 348159
* [X86] Add DAG combine to combine a v8i32->v8i16 truncate with a packuswb ↵Craig Topper2018-12-032-0/+40
| | | | | | | | | | | | | | | | | | | that truncates v8i16->v8i8. Summary: Under -x86-experimental-vector-widening-legalization, fp_to_uint/fp_to_sint with a smaller than 128 bit vector type results are custom type legalized by promoting the result to a 128 bit vector by promoting the elements, inserting an assertzext/assertsext, then truncating back to original type. The truncate will be further legalizdd to a pack shuffle. In the case of a v8i8 result type, we'll end up with a v8i16 fp_to_sint. This will need to be further legalized during vector op legalization by promoting to v8i32 and then truncating again. Under avx2 this produces good code with two pack instructions, but Under avx512 this will result in a truncate instruction and a packuswb instruction. But we should be able to get away with a single truncate instruction. The other option is to promote all the way to vXi32 result type during the first type legalization. But in some experimentation that seemed to require more work to produce good code for other configurations. Reviewers: RKSimon, spatel Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54836 llvm-svn: 348158
* Fix non-modular build.Adrian Prantl2018-12-031-0/+4
| | | | llvm-svn: 348157
* Update Diagnostic handling for changes in CFE.Adrian Prantl2018-12-031-11/+27
| | | | | | | | | | | The clang frontend no longer emits the current working directory for DIFiles containing an absolute path in the filename: and will move the common prefix between current working directory and the file into the directory: component. https://reviews.llvm.org/D55085 llvm-svn: 348155
* [CmpInstAnalysis] fix formatting; NFCSanjay Patel2018-12-032-9/+9
| | | | | | | | There are potential improvements to the structure of this API raised by D54994, but remove some cosmetic blemishes before making any functional changes. llvm-svn: 348149
* Fixing -print-module-scope for legacy SCC passesFedor Sergeev2018-12-031-4/+21
| | | | | | | | | | It appears that print-module-scope was not implemented for legacy SCC passes. Fixed to print a whole module instead of just current SCC. Reviewed By: mkazantsev Differential Revision: https://reviews.llvm.org/D54793 llvm-svn: 348144
* [SystemZ::TTI] Return zero cost for ICmp that becomes Load And Test.Jonas Paulsson2018-12-031-0/+10
| | | | | | | | | | | | | A loaded value with multiple users compared with 0 will become a load and test single instruction. The load is not folded in this case (multiple users), but the compare instruction is eliminated. This patch returns 0 cost for the icmp in these cases. Review: Ulrich Weigand https://reviews.llvm.org/D55111 llvm-svn: 348141
* [AArch64] Add command-line option for SSBSPablo Barrio2018-12-033-3/+8
| | | | | | | | | | | | | | | | | | | | | Summary: SSBS (Speculative Store Bypass Safe) is only mandatory from 8.5 onwards but is optional from Armv8.0-A. This patch adds a command line option to enable SSBS, as it was previously only possible to enable by selecting -march=armv8.5-a. Similar patch upstream in GNU binutils: https://sourceware.org/ml/binutils/2018-09/msg00274.html Reviewers: olista01, samparker, aemerson Reviewed By: samparker Subscribers: javed.absar, kristof.beyls, kristina, llvm-commits Differential Revision: https://reviews.llvm.org/D54629 llvm-svn: 348137
* [AMDGPU] Add sdwa support for ADD|SUB U64 decomposed PseudosRon Lieberman2018-12-032-2/+99
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The introduction of S_{ADD|SUB}_U64_PSEUDO instructions which are decomposed into VOP3 instruction pairs for S_ADD_U64_PSEUDO: V_ADD_I32_e64 V_ADDC_U32_e64 and for S_SUB_U64_PSEUDO V_SUB_I32_e64 V_SUBB_U32_e64 preclude the use of SDWA to encode a constant. SDWA: Sub-Dword addressing is supported on VOP1 and VOP2 instructions, but not on VOP3 instructions. We desire to fold the bit-and operand into the instruction encoding for the V_ADD_I32 instruction. This requires that we transform the VOP3 into a VOP2 form of the instruction (_e32). %19:vgpr_32 = V_AND_B32_e32 255, killed %16:vgpr_32, implicit $exec %47:vgpr_32, %49:sreg_64_xexec = V_ADD_I32_e64 %26.sub0:vreg_64, %19:vgpr_32, implicit $exec %48:vgpr_32, dead %50:sreg_64_xexec = V_ADDC_U32_e64 %26.sub1:vreg_64, %54:vgpr_32, killed %49:sreg_64_xexec, implicit $exec which then allows the SDWA encoding and becomes %47:vgpr_32 = V_ADD_I32_sdwa 0, %26.sub0:vreg_64, 0, killed %16:vgpr_32, 0, 6, 0, 6, 0, implicit-def $vcc, implicit $exec %48:vgpr_32 = V_ADDC_U32_e32 0, %26.sub1:vreg_64, implicit-def $vcc, implicit $vcc, implicit $exec Differential Revision: https://reviews.llvm.org/D54882 llvm-svn: 348132
* ARM: use target-specific SUBS node when combining cmp with cmov.Tim Northover2018-12-035-11/+42
| | | | | | | | | | | This has two positive effects. First, using a custom node prevents recombination leading to an infinite loop since the output DAG is notionally a little more complex than the input one. Using a flag-setting instruction also allows the subtraction to be folded with the related comparison more easily. https://reviews.llvm.org/D53190 llvm-svn: 348122
* [NFC][AArch64] Split out backend featuresDiogo N. Sampaio2018-12-036-72/+297
| | | | | | | | | | | | | | | | | | | | | This patch splits backend features currently hidden behind architecture versions. For example, currently the only way to activate complex numbers extension is targeting an v8.3 architecture, where after the patch this extension can be added separately. This refactoring is required by the new command lines proposal: http://lists.llvm.org/pipermail/llvm-dev/2018-September/126346.html Reviewers: DavidSpickett, olista01, t.p.northover Subscribers: kristof.beyls, bryanpkc, javed.absar, pbarrio Differential revision: https://reviews.llvm.org/D54633 llvm-svn: 348121
* [llvm-dwarfdump] - Stop printing the bogus empty section name on invalid dwarf.George Rimar2018-12-031-2/+2
| | | | | | | | | | | | | | | | | | | | | When there is no .debug_addr section for some reason, llvm-dwarfdump would print the bogus empty section name when dumping ranges in .debug_info: DW_AT_ranges [DW_FORM_rnglistx] (indexed (0x0) rangelist = 0x00000004 [0x0000000000000000, 0x0000000000000001) "" [0x0000000000000000, 0x0000000000000002) "") That happens because of the code which uses 0 (zero) as a section index as a default value. The code should use -1ULL instead because technically 0 is a valid zero section index in ELF and -1ULL is a special constant used that means "no section available". This is mostly a fix for the overall correctness/safety of the code, but a test case is provided too. Differential revision: https://reviews.llvm.org/D55113 llvm-svn: 348115
* [ARM][MC] Move information about variadic register defs into tablegenOliver Stannard2018-12-035-38/+11
| | | | | | | | | | | | | | | | | | | Currently, variadic operands on an MCInst are assumed to be uses, because they come after the defs. However, this is not always the case, for example the Arm/Thumb LDM instructions write to a variable number of registers. This adds a property of instruction definitions which can be used to mark variadic operands as defs. This only affects MCInst, because MachineInstruction already tracks use/def per operand in each instance of the instruction, so can already represent this. This property can then be checked in MCInstrDesc, allowing us to remove some special cases in ARMAsmParser::isITBlockTerminator. Differential revision: https://reviews.llvm.org/D54853 llvm-svn: 348114
* [ARM][Asm] Debug trace for the processInstruction loopOliver Stannard2018-12-032-4/+16
| | | | | | | | | | | | | | | | | | | In the Arm assembly parser, we first match an instruction, then call processInstruction to possibly change it to a different encoding, to match rules in the architecture manual which can't be expressed by the table-generated matcher. This adds debug printing so that this process is visible when using the -debug option. To support this, I've added a new overload of MCInst::dump_pretty which takes the opcode name as a StringRef, since we don't have an InstPrinter instance in the assembly parser. Instead, we can get the same information directly from the MCInstrInfo. Differential revision: https://reviews.llvm.org/D54852 llvm-svn: 348113
* [KMSAN] Enable -msan-handle-asm-conservative by defaultAlexander Potapenko2018-12-031-2/+5
| | | | | | | | | | This change enables conservative assembly instrumentation in KMSAN builds by default. It's still possible to disable it with -msan-handle-asm-conservative=0 if something breaks. It's now impossible to enable conservative instrumentation for userspace builds, but it's not used anyway. llvm-svn: 348112
* [ARM] FP16: support vld1.16 for vector loads with post-incrementSjoerd Meijer2018-12-031-0/+2
| | | | | | Differential Revision: https://reviews.llvm.org/D55112 llvm-svn: 348110
* [PowerPC] Fix inconsistent ImmMustBeMultipleOf for same instructionKang Zhang2018-12-031-4/+12
| | | | | | | | | | | | | Summary: There are 4 instructions which have Inconsistent ImmMustBeMultipleOf in the function PPCInstrInfo::instrHasImmForm, they are LFS, LFD, STFS, STFD. These four instructions should set the ImmMustBeMultipleOf to 1 instead of 4. Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D54738 llvm-svn: 348109
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