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| author | Sjoerd Meijer <sjoerd.meijer@arm.com> | 2018-12-03 08:26:34 +0000 |
|---|---|---|
| committer | Sjoerd Meijer <sjoerd.meijer@arm.com> | 2018-12-03 08:26:34 +0000 |
| commit | 5afc957eba60e9685be1d55e261b6605dc95133d (patch) | |
| tree | 09732f38e1932ae00b7555f4fca9997cb7036ce0 /llvm/lib | |
| parent | 51986417f9c412b321e3831afc2af79ac7fdcd62 (diff) | |
| download | bcm5719-llvm-5afc957eba60e9685be1d55e261b6605dc95133d.tar.gz bcm5719-llvm-5afc957eba60e9685be1d55e261b6605dc95133d.zip | |
[ARM] FP16: support vld1.16 for vector loads with post-increment
Differential Revision: https://reviews.llvm.org/D55112
llvm-svn: 348110
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp index 77622567d4b..8e0e8238825 100644 --- a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp +++ b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp @@ -1763,12 +1763,14 @@ void ARMDAGToDAGISel::SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs, default: llvm_unreachable("unhandled vld type"); // Double-register operations: case MVT::v8i8: OpcodeIndex = 0; break; + case MVT::v4f16: case MVT::v4i16: OpcodeIndex = 1; break; case MVT::v2f32: case MVT::v2i32: OpcodeIndex = 2; break; case MVT::v1i64: OpcodeIndex = 3; break; // Quad-register operations: case MVT::v16i8: OpcodeIndex = 0; break; + case MVT::v8f16: case MVT::v8i16: OpcodeIndex = 1; break; case MVT::v4f32: case MVT::v4i32: OpcodeIndex = 2; break; |
