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* Start using LexicalScopes utility. No intetional functionality change.Devang Patel2011-08-102-526/+113
| | | | llvm-svn: 137246
* Fix typo. Not quite sure how that slipped in there.Jim Grosbach2011-08-101-3/+3
| | | | llvm-svn: 137245
* ARM LDRD(immediate) assembly parsing and encoding support.Jim Grosbach2011-08-102-7/+104
| | | | llvm-svn: 137244
* When performing a truncating store, it is sometimes possible to rearrange theNadav Rotem2011-08-101-2/+79
| | | | | | | | data in-register prior to saving to memory. When we reorder the data in memory we prevent the need to save multiple scalars to memory, making a single regular store. llvm-svn: 137238
* Provide utility to extract and use lexical scoping information from machine ↵Devang Patel2011-08-102-0/+306
| | | | | | instructions. llvm-svn: 137237
* Add initial support for decoding NEON instructions in Thumb2 mode.Owen Anderson2011-08-102-4/+56
| | | | llvm-svn: 137236
* Comments. Thanks for the spell check Nick!Andrew Trick2011-08-102-4/+4
| | | | | | Also, my apologies for spoiling the autocomplete on SimplifyInstructions.cpp. I couldn't think of a better filename. llvm-svn: 137229
* The following X86 pattern is incorrect:Bruno Cardoso Lopes2011-08-101-7/+0
| | | | | | | | | def : Pat<(X86Movss VR128:$src1, (bc_v4i32 (v2i64 (load addr:$src2)))), (MOVLPSrm VR128:$src1, addr:$src2)>; This matches a MOVSS dag with a MOVLPS instruction. However, MOVSS will replace only the low 32 bits of the register, while the MOVLPS instruction will replace the low 64 bits. A testcase is added and illustrates the bug and also modified the one that was already present. Patch by Tanya Lattner. llvm-svn: 137227
* Whitespace.Eli Friedman2011-08-101-1/+1
| | | | llvm-svn: 137226
* Tabs --> spaces.Owen Anderson2011-08-101-2/+2
| | | | llvm-svn: 137225
* Cleanups based on Nick Lewycky's feedback.Owen Anderson2011-08-101-19/+22
| | | | llvm-svn: 137224
* Rewrite some ARM InstrInfo functions to be most accepting of arbitrary ↵Owen Anderson2011-08-101-110/+115
| | | | | | register subclasses. Hopefully this fixes some buildbots. llvm-svn: 137223
* Add support for the R and Q constraints.Rafael Espindola2011-08-101-2/+22
| | | | llvm-svn: 137217
* Clarify a comment.Bob Wilson2011-08-101-1/+3
| | | | llvm-svn: 137204
* Invoke SimplifyIndVar when we partially unroll a loop. Fixes PR10534.Andrew Trick2011-08-102-5/+25
| | | | llvm-svn: 137203
* Cleanup. Make ScalarEvolution an explicit argument of theAndrew Trick2011-08-102-11/+11
| | | | | | SimplifyIndVar utility since it is required. llvm-svn: 137202
* SimplifyIndVar: make foldIVUser iterative to fold a chain of operands.Andrew Trick2011-08-101-12/+26
| | | | llvm-svn: 137199
* Update CMake build.Benjamin Kramer2011-08-101-0/+1
| | | | llvm-svn: 137198
* Added a SimplifyIndVar utility to simplify induction variable usersAndrew Trick2011-08-102-328/+461
| | | | | | | | | | | | | | | | based on ScalarEvolution without changing the induction variable phis. This utility is the main tool of IndVarSimplifyPass, but the pass also restructures induction variables in strange ways that are sensitive to pass ordering. This provides a way for other loop passes to simplify new uses of induction variables created during transformation. The utility may be used by any pass that preserves ScalarEvolution. Soon LoopUnroll will use it. The net effect in this checkin is to cleanup the IndVarSimplify pass by factoring out the SimplifyIndVar algorithm into a standalone utility. llvm-svn: 137197
* Cleanup. Added LoopBlocksDFS::perform for simple clients.Andrew Trick2011-08-102-7/+15
| | | | llvm-svn: 137195
* Fix a bug in vpermilps mask checking. Fix PR10560Bruno Cardoso Lopes2011-08-101-3/+6
| | | | llvm-svn: 137194
* Fix the LoopUnroller to handle nontrivial loops and partial unrolling.Andrew Trick2011-08-101-52/+60
| | | | | | | | | | These are not individual bug fixes. I had to rewrite a good chunk of the unroller to make it sane. I think it was getting lucky on trivial completely unrolled loops with no early exits. I included some fairly simple unit tests for partial unrolling. I didn't do much stress testing, so it may not be perfect, but should be usable now. llvm-svn: 137190
* Push GPRnopc through a large number of instruction definitions to tighten ↵Owen Anderson2011-08-102-87/+110
| | | | | | operand decoding. llvm-svn: 137189
* Trim an unneeded header.Jakob Stoklund Olesen2011-08-092-0/+2
| | | | llvm-svn: 137184
* Promote VMOVS to VMOVD when possible.Jakob Stoklund Olesen2011-08-091-2/+29
| | | | | | | | | | | | | | | | | | | | | | | | | On Cortex-A8, we use the NEON v2f32 instructions for f32 arithmetic. For better latency, we also send D-register copies down the NEON pipeline by translating them to vorr instructions. This patch promotes even S-register copies to D-register copies when possible so they can also go down the NEON pipeline. Example: vldr.32 s0, LCPI0_0 loop: vorr d1, d0, d0 loop2: ... vadd.f32 d1, d1, d16 The vorr instruction looked like this after regalloc: %S2<def> = COPY %S0, %D1<imp-def> Copies involving odd S-registers, and copies that don't define the full D-register are left alone. llvm-svn: 137182
* Tighten operand checking of register-shifted-register operands.Owen Anderson2011-08-092-5/+5
| | | | llvm-svn: 137180
* Add 256-bit support for v8i32, v4i64 and v4f64 ISD::SELECT. Fix PR10556Bruno Cardoso Lopes2011-08-092-0/+25
| | | | llvm-svn: 137179
* Tighten operand checking on memory barrier instructions.Owen Anderson2011-08-092-2/+25
| | | | llvm-svn: 137176
* VMCore/BasicBlock.cpp: Don't assume BasicBlock::iterator might end with a ↵NAKAMURA Takumi2011-08-091-2/+6
| | | | | | | | | | non-PHInode Instruction in successors. Frontends(eg. clang) might pass incomplete form of IR, to step off the way beyond iterator end. In the case I had met, it took infinite loop due to meeting bogus PHInode. Thanks to Jay Foad and John McCall. llvm-svn: 137175
* Fix whitespace.NAKAMURA Takumi2011-08-091-4/+4
| | | | llvm-svn: 137174
* Tighten operand checking on CPS instructions.Owen Anderson2011-08-092-0/+7
| | | | llvm-svn: 137172
* Representation of 'atomic load' and 'atomic store' in IR.Eli Friedman2011-08-098-40/+248
| | | | llvm-svn: 137170
* Create a new register class for the set of all GPRs except the PC. Use it ↵Owen Anderson2011-08-093-3/+21
| | | | | | to tighten our decoding of BFI. llvm-svn: 137168
* Add v16i16 and v32i8 store patternsBruno Cardoso Lopes2011-08-091-0/+8
| | | | llvm-svn: 137166
* Fix 80-column violations.Chad Rosier2011-08-091-3/+3
| | | | llvm-svn: 137163
* Use fp unpack instructions to unpack int types. Until we have AVX2, thisBruno Cardoso Lopes2011-08-092-8/+34
| | | | | | is the best we can do for these patterns. This fix PR10554. llvm-svn: 137161
* Fix a couple ridiculous copy-paste errors. rdar://9914773 .Eli Friedman2011-08-091-2/+2
| | | | llvm-svn: 137160
* Add a C interface to PassManagerBuilder. It is missing the addExtensionRafael Espindola2011-08-091-0/+80
| | | | | | | functionality since in the C api a pass is created and added to a pass manager in a single call. llvm-svn: 137159
* Don't truncate MachO addresses.Jim Grosbach2011-08-091-1/+1
| | | | | | | | | | | | | | Assigned symbol addresses get truncated to 32-bits, even on 64-bit platforms. That's obviously bogus. For example, .globl _foo .equ _foo, 0x987654321ULL rdar://9922863 llvm-svn: 137158
* ARM Disassembler: sign extend branch immediates.Benjamin Kramer2011-08-091-2/+2
| | | | | | Not sure about BLXi, but this is what the old disassembler did. llvm-svn: 137156
* Silence an false-positive warning.Owen Anderson2011-08-091-1/+1
| | | | llvm-svn: 137154
* Don't generate the old-style disassembler in CMake builds either.Owen Anderson2011-08-091-1/+0
| | | | llvm-svn: 137153
* The new ARM disassembler disassembles "bx lr" as a special BX_ret ↵Benjamin Kramer2011-08-091-10/+0
| | | | | | instruction so target specific analysis isn't needed anymore. llvm-svn: 137151
* Don't continue generating the old-style decoder file.Owen Anderson2011-08-091-3/+2
| | | | llvm-svn: 137150
* ARM fix typo in pre-indexed store lowering.Jim Grosbach2011-08-091-1/+1
| | | | | | rdar://9915869 llvm-svn: 137148
* Attempt to fix CMake build.Owen Anderson2011-08-091-0/+1
| | | | llvm-svn: 137147
* Tighten Thumb1 branch predicate decoding.Owen Anderson2011-08-091-0/+3
| | | | llvm-svn: 137146
* Replace the existing ARM disassembler with a new one based on the ↵Owen Anderson2011-08-0912-7229/+2417
| | | | | | | | | | FixedLenDecoderEmitter. This new disassembler can correctly decode all the testcases that the old one did, though some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in operand checking as the old one was. llvm-svn: 137144
* Put Darwin-specific code inside an __APPLE__ ifdef.Bob Wilson2011-08-091-0/+2
| | | | llvm-svn: 137137
* Revert r137134. It breaks some code as Eli pointed out.Bill Wendling2011-08-091-1/+1
| | | | llvm-svn: 137135
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