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* [SimpleLoopUnswitch] Unswitch by experimental.guard intrinsicsMax Kazantsev2018-10-261-2/+107
| | | | | | | | | | | | | | | | | | This patch adds support of `llvm.experimental.guard` intrinsics to non-trivial simple loop unswitching. These intrinsics represent implicit control flow which has pretty much the same semantics as usual conditional branches. The algorithm of dealing with them is following: - Consider guards as unswitching candidates; - If a guard is considered the best candidate, turn it into a branch; - Apply normal unswitching algorithm on this branch. The patch has no compile time effect on code that does not contain any guards. Differential Revision: https://reviews.llvm.org/D53744 Reviewed By: chandlerc llvm-svn: 345387
* [AMDGPU] Add a pass to promote bitcast callsScott Linder2018-10-264-0/+74
| | | | | | | | | | | | AMDGPU currently only supports direct calls, but at lower optimisation levels it fails to lower statically direct calls which appear indirect due to a bitcast. Add a pass to visit all CallSites and use CallPromotionUtils to "devirtualize" calls. Differential Revision: https://reviews.llvm.org/D52741 llvm-svn: 345382
* [Codegen] - Implement basic .debug_loclists section emission (DWARF5).George Rimar2018-10-265-53/+157
| | | | | | | | | .debug_loclists is the DWARF 5 version of the .debug_loc. With that patch, it will be emitted when DWARF 5 is used. Differential revision: https://reviews.llvm.org/D53365 llvm-svn: 345377
* [SimpleLoopUnswitch] Make all checks before actual non-trivial unswitchMax Kazantsev2018-10-261-18/+20
| | | | | | | | | | | We should be able to make all relevant checks before we actually start the non-trivial unswitching, so that we could guarantee that once we have started the transform, it will always succeed. Reviewed By: chandlerc Differential Revision: https://reviews.llvm.org/D53747 llvm-svn: 345375
* [SystemZ] Fix -Wcovered-switch-default as coding standard regulatesFangrui Song2018-10-261-1/+0
| | | | llvm-svn: 345369
* [PowerPC] Fix some missed optimization opportunities in combineSetCCLi Jia He2018-10-262-0/+35
| | | | | | | | | | | For both operands are bool, short, int, long, long long, add the following optimization. 1. 0-x == y --> x+y ==0 2. 0-x != y --> x+y != 0 Review: nemanjai Differential Revision: https://reviews.llvm.org/D53360 llvm-svn: 345366
* [PowerPC] Keep vector int to fp conversions in vector domainNemanja Ivanovic2018-10-262-0/+71
| | | | | | | | | | | | At present a v2i16 -> v2f64 convert is implemented by extracts to scalar, scalar converts, and merge back into a vector. Use vector converts instead, with the int data permuted into the proper position and extended if necessary. Patch by RolandF. Differential revision: https://reviews.llvm.org/D53346 llvm-svn: 345361
* Add dependency from SystemZAsmParser to SystemZAsmPrinter after rL345349Fangrui Song2018-10-261-1/+1
| | | | | | This fixes -DBUILD_SHARED_LIBS=on build. The dependency is similar to that of X86's. llvm-svn: 345358
* Revert "[AArch64] Create proper memoperand for multi-vector stores"Vlad Tsyrklevich2018-10-261-1/+1
| | | | | | | This reverts commit r345315, it was causing test failures on sanitizer-x86_64-linux-fast. llvm-svn: 345356
* [SystemZ] Implement SystemZOperand::print()Jonas Paulsson2018-10-261-1/+66
| | | | | | | | | | | | | SystemZAsmParser can now handle -debug by printing the operands neatly to the output stream. Before this patch this lead to an llvm_unreachable(). It seems that now '-mllvm -debug' does not cause any crashes anywhere (at least not on SPEC). Review: Ulrich Weigand https://reviews.llvm.org/D53328 llvm-svn: 345349
* [SystemZ] Pass the DAG pointer from SystemZAddressingMode::dump().Jonas Paulsson2018-10-261-4/+4
| | | | | | | | | | | | | In order to print the IR slot number for the memory operand, the DAG pointer must be passed to SDNode::dump(). The isel-debug.ll test updated to also check for the IR Value reference being printed correctly. Review: Ulrich Weigand https://reviews.llvm.org/D53333 llvm-svn: 345347
* Reland "[WebAssembly] LSDA info generation"Heejin Ahn2018-10-2516-62/+264
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This adds support for LSDA (exception table) generation for wasm EH. Wasm EH mostly follows the structure of Itanium-style exception tables, with one exception: a call site table entry in wasm EH corresponds to not a call site but a landing pad. In wasm EH, the VM is responsible for stack unwinding. After an exception occurs and the stack is unwound, the control flow is transferred to wasm 'catch' instruction by the VM, after which the personality function is called from the compiler-generated code. (Refer to WasmEHPrepare pass for more information on this part.) This patch: - Changes wasm.landingpad.index intrinsic to take a token argument, to make this 1:1 match with a catchpad instruction - Stores landingpad index info and catch type info MachineFunction in before instruction selection - Lowers wasm.lsda intrinsic to an MCSymbol pointing to the start of an exception table - Adds WasmException class with overridden methods for table generation - Adds support for LSDA section in Wasm object writer Reviewers: dschuff, sbc100, rnk Subscribers: mgorny, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52748 llvm-svn: 345345
* [WebAssembly] Support EH instructions in InstPrinterHeejin Ahn2018-10-252-9/+66
| | | | | | | | | | | | Summary: This adds support for exception handling instructions to InstPrinter. Reviewers: dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D53634 llvm-svn: 345343
* Fix in MachineOperand::printIRValueReference().Jonas Paulsson2018-10-251-1/+2
| | | | | | | | | | | Handle the case where getCurrentFunction() returns nullptr by passing -1 to printIRSlotNumber(). This will result in <badref> being printed instead of an assertion failure. Review: Francis Visoiu Mistrih https://reviews.llvm.org/D53333 llvm-svn: 345342
* [AArch64] Implement FP16FML intrinsicsBryan Chan2018-10-252-25/+45
| | | | | | | | | | | | Add LLVM intrinsics for the ARMv8.2-A FP16FML vector-form instructions. Add a DAG pattern to define the indexed-form intrinsics in terms of the vector-form ones, similarly to how the Dot Product intrinsics were implemented. Based on a patch by Gao Yiling. Differential Revision: https://reviews.llvm.org/D53632 llvm-svn: 345337
* Address commentsHeejin Ahn2018-10-251-4/+2
| | | | | | | - Add llvm-mc test case (and delete the old one) - Change report_fatal_error to assertions llvm-svn: 345334
* [WebAssembly] Error out when block/loop markers mismatchHeejin Ahn2018-10-251-7/+7
| | | | | | | | | | | | | | | | Summary: Currently InstPrinter ignores if there are mismatches between block/loop and end markers by skipping the case if ControlFlowStack is empty. I guess it is better to explicitly error out in this case, because this signals invalid input. Reviewers: aardappel Subscribers: dschuff, sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D53620 llvm-svn: 345333
* [SystemZ] NFC reformatting in SystemZTargetTransformInfo.cppJonas Paulsson2018-10-251-5/+7
| | | | | | Some lines more than 80 characters long reformatted. llvm-svn: 345331
* [SystemZ] Improve getMemoryOpCost() to find foldable loads that are converted.Jonas Paulsson2018-10-252-41/+90
| | | | | | | | | | | | | The SystemZ backend can do arithmetic of memory by loading and then extending one of the operands. Similarly, a load + truncate can be folded into an operand. This patch improves the SystemZ TTI cost function to recognize this. Review: Ulrich Weigand https://reviews.llvm.org/D52692 llvm-svn: 345327
* DebugInfo: Explain why DW_LLE_(GNU_)startx_length is usedDavid Blaikie2018-10-251-4/+7
| | | | | | | | | | This isn't the most object-size efficient encoding, but it's the only one GDB supports for the pre-standard fission format. I've written fixes for this twice now... - so perhaps this comment will help me remember why neither of these have been committed and why I shouldn't try to write a third fix another year from now... llvm-svn: 345326
* [SystemZ] Improve handling and cost estimates of vector integer div/remJonas Paulsson2018-10-253-39/+69
| | | | | | | | | | | | | | | Enable the DAG optimization that converts vector div/rem with constants into multiply+shifts sequences by expanding them early. This is needed since ISD::SMUL_LOHI is 'Custom' lowered on SystemZ, and will therefore not be available to BuildSDIV after legalization. Better cost values for these instructions based on how they will be implemented (a constant divisor is cheaper). Review: Ulrich Weigand https://reviews.llvm.org/D53196 llvm-svn: 345321
* llvm-dwarfdump: loclists: Don't expect an (albeit empty) expression for ↵David Blaikie2018-10-251-6/+8
| | | | | | LLE_base_address llvm-svn: 345320
* [Pipeliner] Ignore Artificial dependences while computing recurrences.Sumanth Gundapaneni2018-10-251-3/+3
| | | | | | | | | | The artificial dependencies are not real dependencies. In some cases, they form circuits with bigger MII. However, they are used to schedule instructions better. Differential Revision: https://reviews.llvm.org/D53450 llvm-svn: 345319
* [Pipeliner] Remove the unneeded include header(NFC).Sumanth Gundapaneni2018-10-251-1/+0
| | | | | | Differential Revision: https://reviews.llvm.org/D53451 llvm-svn: 345318
* [X86] Change X86 backend to look for 'min-legal-vector-width' attribute ↵Craig Topper2018-10-251-4/+5
| | | | | | | | | | | | instead of 'required-vector-width' when determining whether 512-bit vectors should be legal. The required-vector-width attribute was only used for backend testing and has never been generated by clang. I believe clang is now generating min-legal-vector-width for vector uses in user code. With this I believe passing -mprefer-vector-width=256 to clang should prevent use of zmm registers in the generated assembly unless the user used a 512-bit intrinsic in their source code. llvm-svn: 345317
* [AArch64] Create proper memoperand for multi-vector storesDavid Greene2018-10-251-1/+1
| | | | | | | | | | Include all of the store's source vector operands when creating the MachineMemOperand. Previously, we were missing the first operand, making the store size seem smaller than it really is. Differential Revision: https://reviews.llvm.org/D52816 llvm-svn: 345315
* [WebAssembly] Use target-independent saturating addThomas Lively2018-10-252-2/+8
| | | | | | | | | | Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D53721 llvm-svn: 345299
* [FPEnv] Last BinaryOperator::isFNeg(...) to m_FNeg(...) changesCameron McInally2018-10-252-7/+11
| | | | | | | | | Replacing BinaryOperator::isFNeg(...) to avoid regressions when we separate FNeg from the FSub IR instruction. Differential Revision: https://reviews.llvm.org/D53650 llvm-svn: 345295
* [GlobalISel] LegalizerHelper: Fix the incorrect alignment when splitting ↵Volkan Keles2018-10-251-6/+6
| | | | | | | | | | | | | | loads/stores in narrowScalar Reviewers: dsanders, bogner, jpaquette, aemerson, ab, paquette Reviewed By: dsanders Subscribers: rovka, kristof.beyls, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D53664 llvm-svn: 345292
* [LegalizeDAG] Remove dead SINT_TO_FP legalization codeSimon Pilgrim2018-10-251-54/+19
| | | | | | | | As noticed on D52965, the SINT_TO_FP i64 to f32 legalization code has been dead for years - protected by an assert. Differential Revision: https://reviews.llvm.org/D53703 llvm-svn: 345290
* [GISel] LegalizerInfo: Rename MemDesc::Size to SizeInBits to make the value ↵Volkan Keles2018-10-253-5/+5
| | | | | | | | clearer Requested in D53679. llvm-svn: 345288
* [X86] Remove ProcIntelKNL and replace with a SlowPMADDWD flag to use in the ↵Craig Topper2018-10-253-8/+12
| | | | | | one place it was checked. llvm-svn: 345286
* [X86] Remove some uarch tuning flags from KNL that look to have been ↵Craig Topper2018-10-251-4/+0
| | | | | | | | | | inherited from SNB/IVB incorrectly KNL is based on a modified Silvermont core so I don't think these features apply. I think the LEA flag is probably also wrong, but I'm less sure as I barely understand the 3 LEA flags we have currently. Differential Revision: https://reviews.llvm.org/D53671 llvm-svn: 345285
* [AArch64][GlobalISel] Fix the LegalityPredicate for lowerIf for G_LOAD/G_STOREVolkan Keles2018-10-251-2/+2
| | | | | | | | | | | | | | | | | | | Summary: Currently, Legalizer is trying to lower G_LOAD with a vector type that has more than two elements due to the incorrect LegalityPredicate. This patch fixes the issue by removing the multiplication by 8 as `MemDesc.Size` already contains the size in bits. Reviewers: dsanders, aemerson Reviewed By: dsanders Subscribers: rovka, javed.absar, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D53679 llvm-svn: 345282
* [AArch64] Refactor Exynos feature sets (NFC)Evandro Menezes2018-10-251-12/+6
| | | | llvm-svn: 345279
* [AArch64] Add EXT patterns for 64-bit EXT of a subvector of a 128-bit vectorJohn Brawn2018-10-251-0/+19
| | | | | | | | | | If we have a 64-bit EXT where one of the operands is a subvector of a 128-bit vector then in some cases we can eliminate an extract_subvector by converting to a 128-bit EXT of the 128-bit vector. Differential Revision: https://reviews.llvm.org/D53582 llvm-svn: 345275
* [ARM] Use Cortex-A57 sched model for Cortex-A72Sam Parker2018-10-251-1/+1
| | | | | | | | | | | This mirrors what we already do for AArch64 as the cores are similar. As discussed in the review, enabling the machine scheduler causes more variations in performance changes so it is not enabled for now. This patch improves LNT scores by a geomean of 1.57% at -O3. Differential Revision: https://reviews.llvm.org/D53562 llvm-svn: 345272
* [AArch64] Refactor definition of EXT patterns to use a multiclassJohn Brawn2018-10-251-38/+18
| | | | | | | | | | Using a multiclass reduces duplication, and makes it easier to add new patterns later. This refactoring does add some new patterns, but as far as I can tell there's no IR that will end up triggering them so this is effectively NFC. Differential Revision: https://reviews.llvm.org/D53580 llvm-svn: 345271
* [AArch64] Do 64-bit vector move of 0 and -1 by extracting from the 128-bit moveJohn Brawn2018-10-251-10/+12
| | | | | | | | | | Currently a vector move of 0 or -1 will use different instructions depending on the size of the vector. Using a single instruction (the 128-bit one) for both gives more opportunity for Machine CSE to eliminate instructions. Differential Revision: https://reviews.llvm.org/D53579 llvm-svn: 345270
* [DEBUG_INFO][NVPTX]Fix processing of DBG_VALUES.Alexey Bataev2018-10-251-0/+19
| | | | | | | | | | | | | | | | | Summary: If the instruction in the eliminateFrameIndex function is a DBG_VALUE instruction, it requires special processing. The frame register is set to VRFrame and the offset is based on the object offset. The code is similar to the code used in lib/CodeGen/PrologEpilogInserter.cpp. Reviewers: tra Subscribers: jholewinski, llvm-commits Differential Revision: https://reviews.llvm.org/D53657 llvm-svn: 345269
* [GlobalISel] Use the target preferred type for G_EXTRACT_VECTOR_ELT index.Amara Emerson2018-10-253-1/+33
| | | | | | Allows for better imported pattern re-use. llvm-svn: 345265
* IR: Optimize StructType::get to perform one hash lookup instead of two, NFCIKrasimir Georgiev2018-10-251-7/+14
| | | | | | | | | | | | | | | | | Summary: This function was performing two hash lookups when a new struct type was requested: first checking if it exists and second to insert it. This patch updates the function to perform a single hash lookup in this case by updating the value in the hash table in-place in case the struct type was not there before. Similar to r345151. Reviewers: bkramer Reviewed By: bkramer Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D53689 llvm-svn: 345264
* [CostModel][X86] Add realistic vXi64 uitofp vXf64 costsSimon Pilgrim2018-10-251-7/+6
| | | | | | Match codegen improvements from D53649/rL345256 llvm-svn: 345263
* [RISCV] Use PatFrags for variable shift patternsAlex Bradbury2018-10-251-10/+9
| | | | | | This follows SystemZ and I think is cleaner vs the multiclass. llvm-svn: 345262
* [CostModel][X86] Add realistic i64 uitofp f64 scalar costsSimon Pilgrim2018-10-251-0/+5
| | | | llvm-svn: 345261
* Missing semicolon.Simon Pilgrim2018-10-251-1/+1
| | | | llvm-svn: 345257
* [TargetLowering] Improve vXi64 UINT_TO_FP vXf64 support (P38226)Simon Pilgrim2018-10-253-25/+53
| | | | | | | | | | | | As suggested on D52965, this patch moves the i64 to f64 UINT_TO_FP expansion code from LegalizeDAG into TargetLowering and makes it available to LegalizeVectorOps as well. Not only does this help perform X86 lowering as a true vectorization instead of (partially vectorized) scalar conversions, it avoids the HADDPD op from the scalar code which can be slow on most targets. The AVX512F does have the vcvtusi2sdq scalar operation but we don't unroll to use it as it seems to only help for the v2f64 case - otherwise the unrolling cost will certainly be too high. My feeling is that we should leave it to the vectorizers - and if it generates the vector UINT_TO_FP we should use it. Differential Revision: https://reviews.llvm.org/D53649 llvm-svn: 345256
* [llvm-dwarfdump] - Fix incorrect parsing of the DW_LLE_startx_lengthGeorge Rimar2018-10-253-8/+25
| | | | | | | | | | | | | | | | | As was already mentioned in comments for D53364, DWARF 5 spec says about DW_LLE_startx_length: "This is a form of bounded location description that has two unsigned ULEB operands. The first value is an address index (into the .debug_addr section) that indicates the beginning of the address range over which the location is valid. The second value is the length of the range. ") Currently, the length is always parsed as U32. Patch change the behavior to parse DW_LLE_startx_length as ULEB128 for DWARF 5 and keeps it as U32 for DWARF4+(pre-DWARF5) for compatibility. Differential revision: https://reviews.llvm.org/D53564 llvm-svn: 345254
* [TTI] Add generic SK_Broadcast shuffle costsSimon Pilgrim2018-10-252-5/+35
| | | | | | | | | | I noticed while fixing PR39368 that we don't have generic shuffle costs for broadcast style shuffles. This patch adds SK_BROADCAST handling, but exposes ARM/AARCH64 lack of handling of this type, which I've added a fix for at the same time. Differential Revision: https://reviews.llvm.org/D53570 llvm-svn: 345253
* [DebugInfo][Dexter] Unreachable line stepped onto after SimplifyCFG.Carlos Alberto Enciso2018-10-252-18/+45
| | | | | | | | When SimplifyCFG changes the PHI node into a select instruction, the debug line records becomes ambiguous. It causes the debugger to display unreachable source lines. Differential Revision: https://reviews.llvm.org/D53287 llvm-svn: 345250
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