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* DAGCombine: Let truncates negate extension through extract-subvectorZvi Rackover2018-01-111-0/+16
| | | | | | | | | | | | | | | | | | | | | | Summary: Fold cases such as: (v8i8 truncate (v8i32 extract_subvector (v16i32 sext (v16i8 V), Idx))) -> (v8i8 extract_subvector (v16i8 V), Idx) This can be generalized to cases where the truncate and extend do not fully cancel each other out, but it may require querying the target about profitability. Reviewers: RKSimon, craig.topper, spatel, efriedma Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41927 llvm-svn: 322300
* [Hexagon] Impose limits on container sizes in HexagonGenInsertKrzysztof Parzyszek2018-01-111-3/+20
| | | | | | | With over 300k virtual registers, the size of the data exceeded 12GB. Impose limits on how much information is collected. llvm-svn: 322299
* [Hexagon] Use SetVector when queuing nodes to scan in selectVectorConstantsKrzysztof Parzyszek2018-01-111-3/+4
| | | | llvm-svn: 322298
* X86: Refactor type-splitting to target-legal size vector to a helper functionZvi Rackover2018-01-111-32/+58
| | | | | | | | | | | | | | Summary: This is a preparatory step for D41811: refactoring code for breaking vector operands of binary operation to legal-types. Reviewers: RKSimon, craig.topper, spatel Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41925 llvm-svn: 322296
* [AArch64] Remove Unsupported = 1 flag for the WriteAtomic WriteRes.Joel Jones2018-01-111-1/+1
| | | | | | | | | | | | | In practice, this patch has no effect on scheduling. There is no test case as there already exists a comprehensive test case for LSE Atomics. Patch by Stefan Teleman Differential Revision: https://reviews.llvm.org/D40694 llvm-svn: 322291
* [InstCombine] Apply the fix from r322284 for sin / cos -> tan tooBenjamin Kramer2018-01-111-2/+3
| | | | llvm-svn: 322285
* [InstCombine] For cos/sin -> tan copy attributes from cos instead of theBenjamin Kramer2018-01-111-2/+3
| | | | | | | | | | | parent function Ideally we should merge the attributes from the functions somehow, but this is obviously an improvement over taking random attributes from the caller which will trip up the verifier if they're nonsensical for an unary intrinsic call. llvm-svn: 322284
* [ValueTracking] recognize min/max-of-min/max with notted ops (PR35875)Sanjay Patel2018-01-111-12/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This was originally planned as the fix for: https://bugs.llvm.org/show_bug.cgi?id=35834 ...but simpler transforms handled that case, so I implemented a lesser solution. It turns out we need to handle the case with 'not' ops too because the real code example that we are trying to solve: https://bugs.llvm.org/show_bug.cgi?id=35875 ...has extra uses of the intermediate values, so we can't rely on smaller canonicalizations to get us to the goal. As with rL321672, I've tried to show every possibility in the codegen tests because that's the simplest way to prove we're doing the right thing in the wide variety of permutations of this pattern. We can also show an InstCombine win because we added a fold for this case in: rL321998 / D41603 An Alive proof for one variant of the pattern to show that the InstCombine and codegen results are correct: https://rise4fun.com/Alive/vd1 Name: min3_nots %nx = xor i8 %x, -1 %ny = xor i8 %y, -1 %nz = xor i8 %z, -1 %cmpxz = icmp slt i8 %nx, %nz %minxz = select i1 %cmpxz, i8 %nx, i8 %nz %cmpyz = icmp slt i8 %ny, %nz %minyz = select i1 %cmpyz, i8 %ny, i8 %nz %cmpyx = icmp slt i8 %y, %x %r = select i1 %cmpyx, i8 %minxz, i8 %minyz => %cmpxyz = icmp slt i8 %minxz, %ny %r = select i1 %cmpxyz, i8 %minxz, i8 %ny Name: min3_nots_alt %nx = xor i8 %x, -1 %ny = xor i8 %y, -1 %nz = xor i8 %z, -1 %cmpxz = icmp slt i8 %nx, %nz %minxz = select i1 %cmpxz, i8 %nx, i8 %nz %cmpyz = icmp slt i8 %ny, %nz %minyz = select i1 %cmpyz, i8 %ny, i8 %nz %cmpyx = icmp slt i8 %y, %x %r = select i1 %cmpyx, i8 %minxz, i8 %minyz => %xz = icmp sgt i8 %x, %z %maxxz = select i1 %xz, i8 %x, i8 %z %xyz = icmp sgt i8 %maxxz, %y %maxxyz = select i1 %xyz, i8 %maxxz, i8 %y %r = xor i8 %maxxyz, -1 llvm-svn: 322283
* [X86][SSE] Add ISD::VECTOR_SHUFFLE to faux shuffle decodingSimon Pilgrim2018-01-111-0/+11
| | | | | | Primarily, this allows us to use the aggressive extraction mechanisms in combineExtractWithShuffle earlier and make use of UNDEF elements that may be lost during lowering. llvm-svn: 322279
* [VectorLegalizer] Remove broken code in ExpandStore.Jonas Paulsson2018-01-111-28/+0
| | | | | | | | | | | | | | The code that is supposed to "Round odd types to the next pow of two" seems broken and as well completely unused (untested). It also seems that ExpandStore really shouldn't ever change the memory VT, which this in fact does. As a first step in fixing the broken handling of vector stores (of irregular types, e.g. an i1 vector), this code is removed. For discussion, see https://bugs.llvm.org/show_bug.cgi?id=35520. Review: Eli Friedman llvm-svn: 322275
* X86: Fix LowerBUILD_VECTORAsVariablePermute for case Src is smaller than IndicesZvi Rackover2018-01-111-0/+5
| | | | | | | | | | | | | | | | | | Summary: As RKSimon suggested in pr35820, in the case that Src is smaller in bit-size than Indices, need to widen Src to avoid type mismatch. Fixes pr35820 Reviewers: RKSimon, craig.topper Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41865 llvm-svn: 322272
* [RISCV] Reserve an emergency spill slot for the register scavenger when ↵Alex Bradbury2018-01-112-0/+22
| | | | | | | | | | | necessary Although the register scavenger can often find a spare register, an emergency spill slot is needed to guarantee success. Reserve this slot in cases where the function is known to have a large stack (meaning the scavenger may be needed when forming stack addresses). llvm-svn: 322269
* Implementation of X86Operand::print.Andrew V. Tischenko2018-01-111-2/+48
| | | | | | Differential Revision: https://reviews.llvm.org/D41610 llvm-svn: 322267
* [Mips] Handle one byte unsupported relocationsStefan Maksimovic2018-01-111-0/+2
| | | | | | | | | Fail gracefully instead of crashing upon encountering this type of relocation. Differential revision: https://reviews.llvm.org/D41857 llvm-svn: 322266
* [X86] Fix unused variable in release builds.Craig Topper2018-01-111-2/+2
| | | | llvm-svn: 322262
* [CodeView] Fix the type for a variadic argumentAaron Smith2018-01-111-0/+12
| | | | | | | | | | | | | | Summary: - MSVC uses the none type for a variadic argument in CodeView - Add a unit test Reviewers: zturner, llvm-commits Reviewed By: zturner Differential Revision: https://reviews.llvm.org/D41931 llvm-svn: 322257
* [InstCombine] Missed optimization in math expression: sin(x) / cos(x) => tan(x)Dmitry Venikov2018-01-113-15/+48
| | | | | | | | | | | | | | Summary: This patch enables folding sin(x) / cos(x) -> tan(x), cos(x) / sin(x) -> 1 / tan(x) under -ffast-math flag Reviewers: hfinkel, spatel Reviewed By: spatel Subscribers: andrew.w.kaylor, efriedma, scanon, llvm-commits Differential Revision: https://reviews.llvm.org/D41286 llvm-svn: 322255
* [X86] Optimize v2i32/v2f32 scatters.Craig Topper2018-01-112-30/+58
| | | | | | | | If the index is v2i64 we can use the scatter instruction that has v4i32/v4f32 data register, v2i64 index, and v2i1 mask. Similar was already done for gather. Implement custom widening for v2i32 data to remove the code that reverses type legalization during lowering. llvm-svn: 322254
* [DWARF][NFC] Overload AsmPrinter::emitDwarfStringOffsets() to take a ↵Wolfgang Pieb2018-01-111-3/+4
| | | | | | | | | | DwarfStringPoolEntry record. Differential Revision: https://reviews.llvm.org/D41920 llvm-svn: 322250
* [NFC] Commit to mention that r322248 is actually made by AndrewScheideckerMarcello Maggioni2018-01-111-1/+1
| | | | llvm-svn: 322249
* [SimplifyCFG] Add cut-off for InitializeUniqueCases.Marcello Maggioni2018-01-111-13/+25
| | | | | | | | | | | | | The function can take a significant amount of time on some complicated test cases, but for the currently only use of the function we can stop the initialization much earlier when we find out we are going to discard the result anyway in the caller of the function. Adding configurable cut-off points so that we avoid wasting time. NFCI. llvm-svn: 322248
* Revert "AArch64: Fix emergency spillslot being out of reach for large ↵Matthias Braun2018-01-108-57/+11
| | | | | | | | | | | | callframes" Revert for now as the testcase is hitting a pre-existing verifier error that manifest as a failure when expensive checks are enabled (or -verify-machineinstrs) is used. This reverts commit r322200. llvm-svn: 322231
* LiveRangeEdit: Inline markDeadRemat() into only user; NFCMatthias Braun2018-01-101-1/+1
| | | | | | | This function was only called from a single place in which we didn't even need the `if (DeadRemats)` check. llvm-svn: 322230
* [X86] Move HasNOPL to a subtarget feature bit. Plumb MCSubtargetInfo through ↵Craig Topper2018-01-104-57/+79
| | | | | | | | | | the MCAsmBackend constructor After D41349, we can no get a MCSubtargetInfo into the MCAsmBackend constructor. This allows us to get NOPL from a subtarget feature rather than a CPU name blacklist. Differential Revision: https://reviews.llvm.org/D41721 llvm-svn: 322227
* LiveRangeEdit: Simplify code; NFCMatthias Braun2018-01-101-12/+14
| | | | | | | | Simplify the code slightly: Instead of creating empty subranges in one case and immediately removing them, do not create them in the first place. llvm-svn: 322226
* [RISCV] Implement support for the BranchRelaxation passAlex Bradbury2018-01-105-9/+133
| | | | | | | | | Branch relaxation is needed to support branch displacements that overflow the instruction's immediate field. Differential Revision: https://reviews.llvm.org/D40830 llvm-svn: 322224
* TargetLoweringBase: The ios simulator has no bzero function.Matthias Braun2018-01-101-3/+12
| | | | | | | | Make sure I really get back to the beahvior before my rewrite in r321035 which turned out not to be completely NFC as I changed the behavior for the ios simulator environment. llvm-svn: 322223
* [RISCV] Implement branch analysisAlex Bradbury2018-01-102-0/+182
| | | | | | | | | This is a prerequisite for the branch relaxation pass, and allows a number of optimisation passes (e.g. BranchFolding and MachineBlockPlacement) to work. Differential Revision: https://reviews.llvm.org/D40808 llvm-svn: 322222
* [RISCV] Add support for llvm.{frameaddress,returnaddress} intrinsicsAlex Bradbury2018-01-102-0/+59
| | | | llvm-svn: 322218
* [RISCV] Add basic support for inline asm constraintsAlex Bradbury2018-01-104-0/+96
| | | | llvm-svn: 322217
* [RISCV] Support stack frames and offsets up to 32-bitsAlex Bradbury2018-01-105-11/+79
| | | | | | Differential Revision: https://reviews.llvm.org/D40807 llvm-svn: 322216
* [RISCV] Support for varargsAlex Bradbury2018-01-104-24/+183
| | | | | | | | | | | | Includes support for expanding va_copy. Also adds support for using 'aligned' registers when necessary for vararg calls, and ensure the frame pointer always points to the bottom of the vararg spill region. This is necessary to ensure that the saved return address and stack pointer are always available at fixed known offsets of the frame pointer. Differential Revision: https://reviews.llvm.org/D40805 llvm-svn: 322215
* Test commit accessScott Linder2018-01-101-2/+2
| | | | llvm-svn: 322213
* [SelectionDAG][X86] Explicitly store the scale in the gather/scatter ISD nodesCraig Topper2018-01-108-40/+66
| | | | | | | | | | Currently we infer the scale at isel time by analyzing whether the base is a constant 0 or not. If it is we assume scale is 1, else we take it from the element size of the pass thru or stored value. This seems a little weird and I think it makes more sense to make it explicit in the DAG rather than doing tricky things in the backend. Most of this patch is just making sure we copy the scale around everywhere. Differential Revision: https://reviews.llvm.org/D40055 llvm-svn: 322210
* [MachineOutliner] Outline ADRPsJessica Paquette2018-01-101-0/+6
| | | | | | | | | ADRP instructions weren't being outlined because they're PC-relative and thus fail the LR checks. This patch adds a special case for ADRPs to getOutliningType to make sure that ADRPs can be outlined and updates the MIR test. llvm-svn: 322207
* AArch64: Fix emergency spillslot being out of reach for large callframesMatthias Braun2018-01-108-11/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | Large callframes (calls with several hundreds or thousands or parameters) could lead to situations in which the emergency spillslot is out of range to be addressed relative to the stack pointer. This commit forces the use of a frame pointer in the presence of large callframes. This commit does several things: - Compute max callframe size at the end of instruction selection. - Add mirFileLoaded target callback. Use it to compute the max callframe size after loading a .mir file when the size wasn't specified in the file. - Let TargetFrameLowering::hasFP() return true if there exists a callframe > 255 bytes. - Always place the emergency spillslot close to FP if we have a frame pointer. - Note that `useFPForScavengingIndex()` would previously return false when a base pointer was available leading to the emergency spillslot getting allocated late (that's the whole effect of this callback). Which made no sense to me so I took this case out: Even though the emergency spillslot is technically not referenced by FP in this case we still want it allocated early. Differential Revision: https://reviews.llvm.org/D40876 llvm-svn: 322200
* [X86][MMX] Pull out common MMX VT test. NFCI.Simon Pilgrim2018-01-101-28/+27
| | | | llvm-svn: 322195
* [AMDGPU][MC][GFX8][GFX9] Added XNACK_MASK supportDmitry Preobrazhensky2018-01-108-5/+54
| | | | | | | | | See bug 35764: https://bugs.llvm.org/show_bug.cgi?id=35764 Differential Revision: https://reviews.llvm.org/D41614 Reviewers: vpykhtin, artem.tamazov, arsenm llvm-svn: 322189
* Avoid inlining if there is byval arguments with non-alloca address spaceBjorn Pettersson2018-01-101-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: After teaching InlineCost more about address spaces () another fault was detected in the inliner. If an argument has the byval attribute the parameter might be copied to an alloca. That part seems to work fine even if the argument has a different address space than the alloca address space. However, if the address spaces differ, then the inlined function still might refer to the parameter using the original address space (the inliner does not handle that situation very well). This patch avoids the problem by simply disallowing inlining when there are byval arguments with address space that differs from the alloca address space. I'm not really sure how to transform the code if we want to get inlining for this situation. I assume that it never has been working, and that the fixes in r321809 just exposed an old problem. Fault found by skatkov (Serguei Katkov). It is mentioned in follow up comments to https://reviews.llvm.org/D40455. Reviewers: skatkov Reviewed By: skatkov Subscribers: uabelho, eraman, llvm-commits, haicheng Differential Revision: https://reviews.llvm.org/D41898 llvm-svn: 322181
* [AArch64][SVE] Asm: Add support for (mov|dup) of scalarSander de Smalen2018-01-102-0/+37
| | | | | | | | | | | | | | Summary: This patch adds support for 'dup' (Scalar -> SVE) and its corresponding 'mov' alias. Reviewers: fhahn, rengolin, evandro, echristo Reviewed By: fhahn Subscribers: aemerson, javed.absar, tschuett, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D41822 llvm-svn: 322172
* [ARM GlobalISel] Map G_FNEG to the FPR bankDiana Picus2018-01-101-1/+2
| | | | llvm-svn: 322169
* [ARM GlobalISel] Legalize G_FNEG for s32 and s64Diana Picus2018-01-101-1/+2
| | | | | | | | | | | | | For hard float, it is legal. For soft float, we need to lower to 0 - x first, and then we can use the libcall for G_FSUB. This is undoing some of the canonicalization performed by the IRTranslator (which introduces G_FNEG when it sees a 0 - x). Ideally, that canonicalization would be performed by a pre-legalizer pass that would allow targets to opt out of this behaviour rather than dance around it in the legalizer. llvm-svn: 322168
* [TableGen][AsmMatcherEmitter] Generate assembler checks for tied operandsSander de Smalen2018-01-101-0/+3
| | | | | | | | | | | | | | | | | | | | Summary: This extends TableGen's AsmMatcherEmitter with code that generates a table with tied-operand constraints. The constraints are checked when parsing the instruction. If an operand is not equal to its tied operand, the assembler will give an error. Patch [2/3] in a series to add operand constraint checks for SVE's predicated ADD/SUB. Reviewers: olista01, rengolin, mcrosier, fhahn, craig.topper, evandro, echristo Reviewed By: fhahn Subscribers: javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D41446 llvm-svn: 322166
* Temporarily revertJonas Paulsson2018-01-101-25/+15
| | | | | | | | "[SystemZ] Check for legality before doing LOAD AND TEST transformations." , due to test failures. llvm-svn: 322165
* [ARM GlobalISel] Legalize s32/s64 G_FCONSTANTDiana Picus2018-01-101-3/+14
| | | | | | | | Legal for hard float. Change to G_CONSTANT for soft float (but preserve the binary representation). llvm-svn: 322164
* [SelectionDAGBuilder] Chain prefetches less aggressively.Jonas Paulsson2018-01-101-7/+13
| | | | | | | | | | | | | Prefetches used to always be chained between any previous and following memory accesses. The problem with this was that later optimizations, such as folding of a load into the user instruction, got disrupted. This patch relaxes the chaining of prefetches in order to remedy this. Reveiw: Hal Finkel https://reviews.llvm.org/D38886 llvm-svn: 322163
* [ARM GlobalISel] Legalize G_CONSTANT for scalars > 32 bitsDiana Picus2018-01-101-3/+4
| | | | | | Make G_CONSTANT narrow for any scalars larger than 32 bits. llvm-svn: 322162
* [SystemZ] Check for legality before doing LOAD AND TEST transformations.Jonas Paulsson2018-01-101-15/+25
| | | | | | | | | | Since a load and test instruction treat its operands as signed, it can only replace a logical compare for EQ/NE uses. Review: Ulrich Weigand https://bugs.llvm.org/show_bug.cgi?id=35662 llvm-svn: 322161
* [ExecutionEngine] Remove an unused variable.Lang Hames2018-01-101-1/+0
| | | | | | | Patch by Evgeniy Tyurin. Thanks Evgeniy! Review: https://reviews.llvm.org/D41431 llvm-svn: 322158
* Add explanatory comment to LoadStoreVectorizer.Justin Lebar2018-01-101-0/+32
| | | | | | | | | | Reviewers: arsenm Subscribers: rengolin, sanjoy, wdng, hiraditya, asbirlea Differential Revision: https://reviews.llvm.org/D41890 llvm-svn: 322157
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