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* [libFuzzer] change the default max_len from 64 to 4096. This will affect ↵Kostya Serebryany2017-06-159-8/+17
| | | | | | cases where libFuzzer is run w/o initial corpus or with a corpus of very small items. llvm-svn: 305521
* Resubmit "[llvm-pdbutil] rewrite the "raw" output style."Zachary Turner2017-06-156-77/+106
| | | | | | | | | This resubmits commit c0c249e9f2ef83e1d1e5f166b50673d92f3579d7. It was broken due to some weird template issues, which have since been fixed. llvm-svn: 305517
* RegScavenging: Add scavengeRegisterBackwards()Matthias Braun2017-06-151-116/+315
| | | | | | | | | | | | | | | | | | Re-apply r276044/r279124. Trying to reproduce or disprove the ppc64 problems reported in the stage2 build last time, which I cannot reproduce right now. This is a variant of scavengeRegister() that works for enterBasicBlockEnd()/backward(). The benefit of the backward mode is that it is not affected by incomplete kill flags. This patch also changes PrologEpilogInserter::doScavengeFrameVirtualRegs() to use the register scavenger in backwards mode. Differential Revision: http://reviews.llvm.org/D21885 llvm-svn: 305516
* [InstCombine] Add two FIXMEs for bad single use checks. NFCCraig Topper2017-06-151-0/+4
| | | | llvm-svn: 305510
* Revert "[llvm-pdbutil] rewrite the "raw" output style."Zachary Turner2017-06-156-106/+77
| | | | | | | | | This reverts commit 83ea17ebf2106859a51fbc2a86031b44d33696ad. This is failing due to some strange template problems, so reverting until it can be straightened out. llvm-svn: 305505
* [DWARF] Removed dead code. The verifier functionality is provided bySpyridoula Gravani2017-06-151-242/+0
| | | | | | the DWARFVerifier class (as it should). llvm-svn: 305503
* Split PGO memory intrinsic optimization into its own source fileTeresa Johnson2017-06-153-361/+420
| | | | | | | | | | | | | | Summary: Split the PGOMemOPSizeOpt pass out from IndirectCallPromotion.cpp into its own file. Reviewers: davidxl Subscribers: mgorny, llvm-commits Differential Revision: https://reviews.llvm.org/D34248 llvm-svn: 305501
* [llvm-pdbutil] rewrite the "raw" output style.Zachary Turner2017-06-156-77/+106
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After some internal discussions, we agreed that the raw output style had outlived its usefulness. It was originally created before we had even thought of dumping to YAML, and it was intended to give us some insight into the internals of a PDB file. Now we have YAML mode which does almost exactly this but is more powerful in that it can round-trip back to a PDB, which the raw mode could not do. So the raw mode had become purely a maintenance burden. One option was to just delete it. However, its original goal was to be as readable as possible while staying close to the "metal" - i.e. presenting the output in a way that maps directly to the underlying file format. We don't actually need that last requirement anymore since it's covered by the yaml mode, so we could repurpose "raw" mode to actually just be as readable as possible. This patch implements about 80% of the functionality previously in raw mode, but in a completely different style that is more akin to what cvdump outputs. Records are very compressed, often times appearing on just one line. One nice thing about this is that it makes full record matching easier, because you can grep for indices, names, and leaf types on a single line often. See the tests for some examples of what the new output looks like. Note that this patch actually regresses the functionality of raw mode in a few areas, but only because the patch was already unreasonably large and going 100% would have been even worse. Specifically, this patch is missing: The ability to dump module debug subsections (checksums, lines, etc) The ability to dump section headers Aside from that everything is here. While goign through the tests fixing them all up, I found many duplicate tests. They've been deleted. In subsequent patches I will go through and re-add the missing functionality. Differential Revision: https://reviews.llvm.org/D34191 llvm-svn: 305495
* DivergencyAnalysis patch for reviewAlexander Timofeev2017-06-155-2/+20
| | | | llvm-svn: 305494
* [InstCombine] Make the context instruction parameter of foldOrOfICmps a ↵Craig Topper2017-06-152-10/+10
| | | | | | reference to discourage passing nullptr and to remove the '&' from all of the call sites. NFC llvm-svn: 305493
* [MachineLICM] Hoist TOC-based address instructionsLei Huang2017-06-153-2/+20
| | | | | | | | | | | | | | | | | | Add condition for MachineLICM to safely hoist instructions that utilize non constant registers that are reserved. On PPC, global variable access is done through the table of contents (TOC) which is always in register X2. The ABI reserves this register in any functions that have calls or access global variables. A call through a function pointer involves saving, changing and restoring this register around the call and thus MachineLICM does not consider it to be invariant. We can however guarantee the register is preserved across the call and thus is invariant. Differential Revision: https://reviews.llvm.org/D33562 llvm-svn: 305490
* Fold variable into assert.Benjamin Kramer2017-06-151-2/+1
| | | | | | Silences an unused variable warning in Release builds. llvm-svn: 305488
* [InstCombine] Handle (iszero(A & K1) | iszero(A & K2)) -> (A & (K1 | K2)) != ↵Craig Topper2017-06-151-20/+14
| | | | | | | | | | | | (K1 | K2) when the one of the Ands is commuted relative to the other Currently we expect A to be on the same side in both Ands but nothing guarantees that. While there also switch to using matchers for some of the code. Differential Revision: https://reviews.llvm.org/D34230 llvm-svn: 305487
* Silence warning with assertions disabled.Peter Collingbourne2017-06-151-0/+1
| | | | llvm-svn: 305485
* ISel: Fix FastISel of swifterror valuesArnold Schwaighofer2017-06-153-14/+125
| | | | | | | | | | | | The code assumed that we process instructions in basic block order. FastISel processes instructions in reverse basic block order. We need to pre-assign virtual registers before selecting otherwise we get def-use relationships wrong. This only affects code with swifterror registers. rdar://32659327 llvm-svn: 305484
* Apply summary-based dead stripping to regular LTO modules with summaries.Peter Collingbourne2017-06-154-95/+153
| | | | | | | | | | | | | | | If a regular LTO module has a summary index, then instead of linking it into the combined regular LTO module right away, add it to the combined summary index and associate it with a special module that represents the combined regular LTO module. Any such modules are linked during LTO::run(), at which time we use the results of summary-based dead stripping to control whether to link prevailing symbols. Differential Revision: https://reviews.llvm.org/D33922 llvm-svn: 305482
* [BasicAA] Don't call isKnownNonEqual if we might be have gone through a PHINode.Craig Topper2017-06-151-4/+18
| | | | | | | | | | | | This is a fix for the test case in PR32314. Basic Alias Analysis can ask if two nodes are known non-equal after looking through a phi node to find a GEP. isAddOfNonZero saw an add of a constant from the same phi and said that its output couldn't be equal. But Basic Alias Analysis was really asking about the value from the previous loop iteration. This patch at least makes that case not happen anymore, I'm not sure if there were still other ways this can fail. As was discussed in the bug, it looks like fixing BasicAA would be difficult so this patch seemed like a possible workaround Differential Revision: https://reviews.llvm.org/D33136 llvm-svn: 305481
* [PowerPC] fix potential verification errors on CFENCE8Hiroshi Inoue2017-06-151-1/+1
| | | | | | | | This patch fixes a potential verification error (64-bit register operands for cmpw) with -verify-machineinstrs. Differential Revision: https://reviews.llvm.org/D34208 llvm-svn: 305479
* [mips] Fix documentation of member variable. NFCI.Simon Dardis2017-06-151-1/+1
| | | | llvm-svn: 305478
* [DAG] As StoreMerge now generates only legal nodes remove unecessary guard ↵Nirav Dave2017-06-151-4/+2
| | | | | | when run post-legalization NFCI. llvm-svn: 305477
* Remove trailing whitespace. NFCI.Simon Pilgrim2017-06-151-1/+1
| | | | llvm-svn: 305476
* [DAG] Defer Pre/Post IndexStore merge to after mergestore. NFCI.Nirav Dave2017-06-151-4/+4
| | | | | | | | In preparation for doing storemerge post-legalization, reorder visitSTORE passes to move pre/post-index combining after store merge. Reordered passes other than store merge are unaffected. llvm-svn: 305473
* [X86][AVX2] Fix issue in lowerV8I16GeneralSingleInputVectorShuffle that was ↵Simon Pilgrim2017-06-151-3/+4
| | | | | | | | | | assuming v8i16 vectors We can use this with v16i16/v32i16 as well. Found during fuzz testing. llvm-svn: 305472
* [AArch64] Add indexed check to splitStores. NFC.Nirav Dave2017-06-151-1/+1
| | | | | | | Add explicit check for unhandled cases in preparation for delaying splitStores to post-legalization. llvm-svn: 305471
* Revert r305465: [X86][AVX512] Improve lowering of AVX512 compare intrinsics ↵Simon Pilgrim2017-06-152-715/+25
| | | | | | | | (remove redundant shift left+right instructions). This is causing windows buildbot failures llvm-svn: 305470
* [DAG] Allow truncated and extend memory operations in Store Merge. NFCI.Nirav Dave2017-06-151-10/+21
| | | | | | | | As all store merges checks are based on the memory operation performed, allow use of truncated stores and extended loads as valid input candidates for merging. llvm-svn: 305468
* [DAG] Make MergeStores generate legalized stores. NFCI.Nirav Dave2017-06-151-4/+21
| | | | | | | Realized merged stores as truncstores if store will be realized as such by legalization. llvm-svn: 305467
* [DAG] Use correct size for truncated store merge of load. NFCI.Nirav Dave2017-06-151-2/+2
| | | | | | | Avoid non-legal memory ops by checking correct size when merging stores of loads into a extload-truncstore pair. llvm-svn: 305466
* [X86][AVX512] Improve lowering of AVX512 compare intrinsics (remove ↵Ayman Musa2017-06-152-25/+715
| | | | | | | | | | | | | | | redundant shift left+right instructions). AVX512 compare instructions return v*i1 types. In cases where the number of elements in the returned value are less than 8, clang adds zeroes to get a mask of v8i1 type. Later on it's replaced with CONCAT_VECTORS, which then is lowered to many DAG nodes including insert/extract element and shift right/left nodes. The fact that AVX512 compare instructions put the result in a k register and zeroes all its upper bits allows us to remove the extra nodes simply by copying the result to the required register class. When lowering, identify these cases and transform them into an INSERT_SUBVECTOR node (marked legal), then catch this pattern in instructions selection phase and transform it into one avx512 cmp instruction. Differential Revision: https://reviews.llvm.org/D33188 llvm-svn: 305465
* [ScalarEvolution] Apply Depth limit to getMulExprMax Kazantsev2017-06-152-60/+83
| | | | | | | | | | | | | | | | | | | | | This is a fix for PR33292 that shows a case of extremely long compilation of a single .c file with clang, with most time spent within SCEV. We have a mechanism of limiting recursion depth for getAddExpr to avoid long analysis in SCEV. However, there are calls from getAddExpr to getMulExpr and back that do not propagate the info about depth. As result of this, a chain getAddExpr -> ... .> getAddExpr -> getMulExpr -> getAddExpr -> ... -> getAddExpr can be extremely long, with every segment of getAddExpr's being up to max depth long. This leads either to long compilation or crash by stack overflow. We face this situation while analyzing big SCEVs in the test of PR33292. This patch applies the same limit on max expression depth for getAddExpr and getMulExpr. Differential Revision: https://reviews.llvm.org/D33984 llvm-svn: 305463
* [ARM] GlobalISel: Add support for i32 moduloDiana Picus2017-06-152-17/+82
| | | | | | | | | | | | | | | | | | Add support for modulo for targets that have hardware division and for those that don't. When hardware division is not available, we have to choose the correct libcall to use. This is generally straightforward, except for AEABI. The AEABI variant is trickier than the other libcalls because it returns { quotient, remainder }, instead of just one value like the other libcalls that we've seen so far. Therefore, we need to use custom lowering for it. However, we don't want to have too much special code, so we refactor the target-independent code in the legalizer by adding a helper for replacing an instruction with a libcall. This helper is used by the legalizer itself when dealing with simple calls, and also by the custom ARM legalization for the more complicated AEABI divmod calls. llvm-svn: 305459
* [ARM] GlobalISel: Lower only homogeneous struct argsDiana Picus2017-06-151-31/+24
| | | | | | | | | | | | | Lowering mixed struct args, params and returns used G_INSERT, which is a bit more convoluted to support through the entire pipeline. Since they don't occur that often in practice, it's probably wiser to leave them out until later. Meanwhile, we can lower homogeneous structs using G_MERGE_VALUES, which has good support in the legalizer. These occur e.g. as the return of __aeabi_idivmod, so it's nice to be able to support them. llvm-svn: 305458
* [AArch64] Enable FeatureFuseAES for the generic processor model.Florian Hahn2017-06-151-0/+1
| | | | | | | | | | | | | | | | | | | | | | | Summary: Scheduling AESE/AESMC and AESD/AESIMC instruction pairs back-to-back gives a double digit speedup on benchmarks using those instructions on Cortex-A processors. In GCC, this optimization is part of the generic processor model as well. This change should not have a major performance impact on processors that do not optimize AES instruction pairs, although I only had access to Cortex-A processors for benchmarking. Reviewers: rengolin, kristof.beyls, javed.absar, evandro, silviu.baranga, MatzeB, mcrosier, joelkevinjones, joel_k_jones, bmakam, t.p.northover Reviewed By: evandro Subscribers: sbaranga, aemerson, llvm-commits Differential Revision: https://reviews.llvm.org/D33836 llvm-svn: 305457
* [mips][microMIPS] Extending size reduction pass with ADDIUSP and ADDIUR1SPZoran Jovanovic2017-06-151-12/+97
| | | | | | | | | | | | Author: milena.vujosevic.janicic Reviewers: sdardis The patch extends size reduction pass for MicroMIPS. The following instructions are examined and transformed, if possible: ADDIU instruction is transformed into 16-bit instruction ADDIUSP ADDIU instruction is transformed into 16-bit instruction ADDIUR1SP Differential Revision: https://reviews.llvm.org/D33887 llvm-svn: 305455
* Fixing section name for Darwin platforms for sanitizer coverageGeorge Karpenkov2017-06-142-2/+2
| | | | | | On Darwin, section names have a 16char length limit. llvm-svn: 305429
* IR: Tweak the API around adding modules to the summary index.Peter Collingbourne2017-06-141-15/+15
| | | | | | | | | | | | | The current name (addModulePath) and return value (ModulePathStringTableTy::iterator) is a little confusing. This API adds a module, not just a path. And the iterator is basically just an implementation detail of the summary index. Address both of those issues by renaming to addModule and introducing a ModuleSummaryIndex::ModuleInfo type that the function returns. Differential Revision: https://reviews.llvm.org/D34124 llvm-svn: 305422
* PredicateInfo: Don't insert conditional info when a conditional branch jumps ↵Daniel Berlin2017-06-141-0/+3
| | | | | | to the same target regardless of condition llvm-svn: 305416
* NewGVN: This is wrong by inspection, it will not cause an issue currently ↵Daniel Berlin2017-06-141-1/+1
| | | | | | due to other limitations, i believe. This also means i can't make a test for it. llvm-svn: 305415
* [x86] avoid unnecessary shuffle mask math in combineX86ShufflesRecursively()Sanjay Patel2017-06-141-6/+7
| | | | | | | | | | | | This is a follow-up to https://reviews.llvm.org/D34174 / https://reviews.llvm.org/rL305398. We mentioned replacing the multiplies with shifts, but the real win seems to be in bypassing the extra ops in the common case when the RootRatio and OpRatio are one. This gives us another 1-2% overall win for the test in PR32037: https://bugs.llvm.org/show_bug.cgi?id=32037 llvm-svn: 305414
* Allow -profile-guided-section-prefix more than onceDavid Callahan2017-06-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: At present, `-profile-guided-section-prefix` is a `cl::Optional` option, which means it demands to be passed exactly zero or one times. Our build system makes it pretty tricky to guarantee this. We often accidentally pass the flag more than once (but always with the same "false" value) which results in an error, after which compilation fails: ``` clang (LLVM option parsing): for the -profile-guided-section-prefix option: may only occur zero or one times! ``` While we work on improving our build system, it also seems reasonable just to allow `-profile-guided-section-prefix` to be passed more than once, by to `cl::ZeroOrMore`. Quoting [[ http://llvm.org/docs/CommandLine.html#controlling-the-number-of-occurrences-required-and-allowed | the documentation ]]: > The cl::ZeroOrMore modifier ... indicates that your program will allow the option to be specified zero or more times. > ... > If an option is specified multiple times for an option of the cl::opt class, only the last value will be retained. Reviewers: danielcdh Reviewed By: danielcdh Subscribers: twoh, david2050, llvm-commits Differential Revision: https://reviews.llvm.org/D34219 llvm-svn: 305413
* [EarlyCSE] Make PhiToCheck in removeMSSA() a set.Davide Italiano2017-06-141-2/+3
| | | | | | | | | | | This way we end up not looking at PHI args already removed. MemSSA now goes through the updater so we can prune it to avoid having redundant MemoryPHI arguments, but that doesn't quite work for the general case. Discussed with Daniel Berlin, fixes PR33406. llvm-svn: 305409
* Hide dbgs() stream for when built with -fmodules.Frederich Munch2017-06-142-1/+16
| | | | | | | | | | | | | | Summary: Make DebugCounter::print and dump methods to be const correct. Reviewers: aprantl Reviewed By: aprantl Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34214 llvm-svn: 305408
* MC, Object: Reserve a section type, SHT_LLVM_ODRTAB, for the ODR table.Peter Collingbourne2017-06-144-0/+6
| | | | | | | | | | | | | | This is part of the ODR checker proposal: http://lists.llvm.org/pipermail/llvm-dev/2017-June/113820.html Per discussion on the gnu-gabi mailing list [1] the section type range 0x6fff4c00..0x6fff4cff is reserved for LLVM. [1] https://sourceware.org/ml/gnu-gabi/2017-q2/msg00030.html Differential Revision: https://reviews.llvm.org/D33978 llvm-svn: 305407
* Specified ReportError as noreturn friendly to old compilers.Galina Kistanova2017-06-141-9/+14
| | | | llvm-svn: 305405
* Test commit - NFC.Lei Huang2017-06-141-1/+1
| | | | | | Modified a comment to confirm commit access functionality. llvm-svn: 305402
* [ValueTracking] Correct early out in computeKnownBitsFromOperator to work ↵Craig Topper2017-06-141-1/+2
| | | | | | | | | | | | with non power of 2 bit widths There's an early out that's trying to detect when we don't know any bits that make up the legal range of a shift. The code subtracts one from BitWidth which creates a mask in the lower bits for power of 2 bit widths. This is then ANDed with the known bits to see if any of those bits are known. If the bit width isn't a power of 2 this creates a non-sensical mask. This patch corrects this by rounding up to a power of 2 before doing the subtract and mask. Differential Revision: https://reviews.llvm.org/D34165 llvm-svn: 305400
* [x86] replace div/rem with shift/mask for better shuffle combining perfSanjay Patel2017-06-141-13/+31
| | | | | | | | | | | | We know that shuffle masks are power-of-2 sizes, but there's no way (?) for LLVM to know that, so hack combineX86ShufflesRecursively() to be much faster by replacing div/rem with shift/mask. This makes the motivating compile-time bug in PR32037 ( https://bugs.llvm.org/show_bug.cgi?id=32037 ) about 9% faster overall. Differential Revision: https://reviews.llvm.org/D34174 llvm-svn: 305398
* [gtest] Create a shared include directory for gtest utilities.Zachary Turner2017-06-147-0/+78
| | | | | | | | | | | | | | | | | | | | | | | Many times unit tests for different libraries would like to use the same helper functions for checking common types of errors. This patch adds a common library with helpers for testing things in Support, and introduces helpers in here for integrating the llvm::Error and llvm::Expected<T> classes with gtest and gmock. Normally, we would just be able to write: EXPECT_THAT(someFunction(), succeeded()); but due to some quirks in llvm::Error's move semantics, gmock doesn't make this easy, so two macros EXPECT_THAT_ERROR() and EXPECT_THAT_EXPECTED() are introduced to gloss over the difficulties. Consider this an exception, and possibly only temporary as we look for ways to improve this. Differential Revision: https://reviews.llvm.org/D33059 llvm-svn: 305395
* Resubmit "[codeview] Make obj2yaml/yaml2obj support .debug$S..."Zachary Turner2017-06-1411-217/+277
| | | | | | | | | This was originally reverted because of some non-deterministic failures on certain buildbots. Luckily ASAN eventually caught this as a stack-use-after-scope, so the fix is included in this patch. llvm-svn: 305393
* Revert "[ARM] Support constant pools in data when generating execute-only code."Alexandros Lamprineas2017-06-143-43/+15
| | | | | | | | | | | This reverts commit 3a204faa093c681a1e96c5e0622f50649b761ee0. I've upset a buildbot which runs the address sanitizer: ERROR: AddressSanitizer: stack-use-after-scope lib/Target/ARM/ARMISelLowering.cpp:2690 That Twine variable is used illegally. llvm-svn: 305390
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