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* Rename ExitCount to BackedgeTakenCount, because that's what it is.James Molloy2015-09-091-8/+9
| | | | | | We called a variable ExitCount, stored the backedge count in it, then redefined it to be the exit count again. llvm-svn: 247140
* Delay predication of stores until near the end of vector code generationJames Molloy2015-09-091-56/+28
| | | | | | | | Predicating stores requires creating extra blocks. It's much cleaner if we do this in one pass instead of mutating the CFG while writing vector instructions. Besides which we can make use of helper functions to update domtree for us, reducing the work we need to do. llvm-svn: 247139
* Fix vector splitting for extract_vector_elt and vector elements of <8-bits.Daniel Sanders2015-09-092-2/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: One of the vector splitting paths for extract_vector_elt tries to lower: define i1 @via_stack_bug(i8 signext %idx) { %1 = extractelement <2 x i1> <i1 false, i1 true>, i8 %idx ret i1 %1 } to: define i1 @via_stack_bug(i8 signext %idx) { %base = alloca <2 x i1> store <2 x i1> <i1 false, i1 true>, <2 x i1>* %base %2 = getelementptr <2 x i1>, <2 x i1>* %base, i32 %idx %3 = load i1, i1* %2 ret i1 %3 } However, the elements of <2 x i1> are not byte-addressible. The result of this is that the getelementptr expands to '%base + %idx * (1 / 8)' which simplifies to '%base + %idx * 0', and then simply '%base' causing all values of %idx to extract element zero. This commit fixes this by promoting the vector elements of <8-bits to i8 before splitting the vector. This fixes a number of test failures in pocl. Reviewers: pekka.jaaskelainen Subscribers: pekka.jaaskelainen, llvm-commits Differential Revision: http://reviews.llvm.org/D12591 llvm-svn: 247128
* Fix a typo I spotted when hacking on SROA. Somewhat alarming thatChandler Carruth2015-09-091-1/+1
| | | | | | nothing broke. llvm-svn: 247127
* [mips][microMIPS] Implement CACHEE and PREFE instructionsZoran Jovanovic2015-09-094-8/+53
| | | | | | Differential Revision: http://reviews.llvm.org/D11628 llvm-svn: 247125
* AMDGPU: Fix not encoding src2 of VOP3b instructionsMatt Arsenault2015-09-091-4/+4
| | | | | | | Broken by r247074. Should include an assembler test, but the assembler is currently broken for VOP3b apparently. llvm-svn: 247123
* [IRCE] Add INITIALIZE_PASS_DEPENDENCY invocations.Sanjoy Das2015-09-091-2/+9
| | | | | | IRCE was just using INITIALIZE_PASS(), which is incorrect. llvm-svn: 247122
* [RuntimeDyld] Add support for MachO x86_64 SUBTRACTOR relocation.Lang Hames2015-09-091-1/+50
| | | | llvm-svn: 247119
* [WebAssembly] Fix lowering of calls with more than one argument.Dan Gohman2015-09-091-2/+5
| | | | llvm-svn: 247118
* SelectionDAG: Support Expand of f16 extloadsMatt Arsenault2015-09-093-30/+27
| | | | | | | | | | Currently this hits an assert that extload should always be supported, which assumes integer extloads. This moves a hack out of SI's argument lowering and is covered by existing tests. llvm-svn: 247113
* [WebAssembly] Implement WebAssemblyInstrInfo::copyPhysRegDan Gohman2015-09-093-22/+38
| | | | llvm-svn: 247110
* Fix typos / grammarMatt Arsenault2015-09-091-26/+26
| | | | llvm-svn: 247109
* [WinEH] Avoid creating MBBs for LLVM BBs that cannot contain codeReid Kleckner2015-09-085-57/+83
| | | | | | | | | | | | | | Typically these are catchpads, which hold data used to decide whether to catch the exception or continue unwinding. We also shouldn't create MBBs for catchendpads, cleanupendpads, or terminatepads, since no real code can live in them. This fixes a problem where MI passes (like the register allocator) would try to put code into catchpad blocks, which are not executed by the runtime. In the new world, blocks ending in invokes now have many possible successors. llvm-svn: 247102
* Re-apply r247080 with order of evaluation fix.Peter Collingbourne2015-09-081-127/+406
| | | | llvm-svn: 247095
* [WinEH] Emit prologues and epilogues for funcletsReid Kleckner2015-09-088-43/+206
| | | | | | | | | | | | | | | | | | | | | | | | Summary: 32-bit funclets have short prologues that allocate enough stack for the largest call in the whole function. The runtime saves CSRs for the funclet. It doesn't restore CSRs after we finally transfer control back to the parent funciton via a CATCHRET, but that's a separate issue. 32-bit funclets also have to adjust the incoming EBP value, which is what llvm.x86.seh.recoverframe does in the old model. 64-bit funclets need to spill CSRs as normal. For simplicity, this just spills the same set of CSRs as the parent function, rather than trying to compute different CSR sets for the parent function and each funclet. 64-bit funclets also allocate enough stack space for the largest outgoing call frame, like 32-bit. Reviewers: majnemer Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D12546 llvm-svn: 247092
* Revert r247080, "LowerBitSets: Extend pass to support functions as bitsetPeter Collingbourne2015-09-081-406/+127
| | | | | | members." as it causes test failures on a number of bots. llvm-svn: 247088
* Fix the PPC CTR Loop pass to look for calls to the intrinsics thatEric Christopher2015-09-081-0/+6
| | | | | | read CTR and count them as reading the CTR. llvm-svn: 247083
* LowerBitSets: Extend pass to support functions as bitset members.Peter Collingbourne2015-09-081-127/+406
| | | | | | | | | | | | | | This change extends the bitset lowering pass to support bitsets that may contain either functions or global variables. A function bitset is lowered to a jump table that is laid out before one of the functions in the bitset. Also add support for non-string bitset identifier names. This allows for distinct metadata nodes to stand in for names with internal linkage, as done in D11857. Differential Revision: http://reviews.llvm.org/D11856 llvm-svn: 247080
* [libFuzzer]Add a test for defeating a hash sum.Ivan Krasin2015-09-083-0/+40
| | | | | | | | | | | | | | | | | Summary: Add a test for a data followed by 4-byte hash value. I use a slightly modified Jenkins hash function, as described in https://en.wikipedia.org/wiki/Jenkins_hash_function The modification is to ensure that hash(zeros) != 0. Reviewers: kcc Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D12648 llvm-svn: 247076
* AMDGPU/SI: Fix input vcc operand for VOP2b instructionsMatt Arsenault2015-09-084-41/+57
| | | | | | | | | Adds vcc to output string input for e32. Allows option of using e64 encoding with assembler. Also fixes these instructions not implicitly reading exec. llvm-svn: 247074
* [NVPTX] Added run NVVMReflect pass to NVPTX back-end.Artem Belevich2015-09-081-0/+1
| | | | | | | | | The pass is needed to remove __nvvm_reflect calls when we link in libdevice bitcode that comes with CUDA. Differential Revision: http://reviews.llvm.org/D11663 llvm-svn: 247072
* x32. Fixes a bug in how struct va_list is initialized in x32Derek Schuff2015-09-081-3/+4
| | | | | | | | | | | | | Summary: This patch modifies X86TargetLowering::LowerVASTART so that struct va_list is initialized with 32 bit pointers in x32. It also includes tests that call @llvm.va_start() for x32. Patch by João Porto Subscribers: llvm-commits, hjl.tools Differential Revision: http://reviews.llvm.org/D12346 llvm-svn: 247069
* [libFuzzer] remove a piece of stale codeKostya Serebryany2015-09-081-41/+1
| | | | llvm-svn: 247067
* [libFuzzer] be more robust when dealing with files on disk (e.g. don't crash ↵Kostya Serebryany2015-09-081-4/+2
| | | | | | if a file was there but disappeared) llvm-svn: 247066
* [WebAssembly] Support running without a register allocator in the default ↵Dan Gohman2015-09-082-51/+19
| | | | | | | | | | | | | CodeGen passes This allows backends which don't use a traditional register allocator, but do need PHI lowering and other passes, to use the default TargetPassConfig::addFastRegAlloc and TargetPassConfig::addOptimizedRegAlloc implementations. Differential Revision: http://reviews.llvm.org/D12691 llvm-svn: 247065
* refactor matches for De Morgan's Laws; NFCISanjay Patel2015-09-081-17/+32
| | | | llvm-svn: 247061
* AMDGPU: Mark s_barrier as a high latency instructionMatt Arsenault2015-09-082-0/+3
| | | | | | | | | | | These were marked as WriteSALU, which is low latency. I'm guessing at the value to use, but it should probably be considered the highest latency instruction. I'm not sure this has any actual effect since hasSideEffects probably is preventing any moving of these. llvm-svn: 247060
* AMDGPU: Fix s_barrier flagsMatt Arsenault2015-09-081-2/+1
| | | | | | | | This should be convergent. This is not a barrier in the isBarrier sense, nor hasCtrlDep. llvm-svn: 247059
* x32. Fixes a bug in i8mem_NOREX declaration.Derek Schuff2015-09-082-6/+17
| | | | | | | | | | | | | | The old implementation assumed LP64 which is broken for x32. Specifically, the MOVE8rm_NOREX and MOVE8mr_NOREX, when selected, would cause a 'Cannot emit physreg copy instruction' error message to be reported. This patch also enable the h-register*ll tests for x32. Differential Revision: http://reviews.llvm.org/D12336 Patch by João Porto llvm-svn: 247058
* AMDGPU: Handle sub of constant for DS offset foldingMatt Arsenault2015-09-081-11/+62
| | | | | | | | | sub C, x - > add (sub 0, x), C for DS offsets. This is mostly to fix regressions that show up when SeparateConstOffsetFromGEP is enabled. llvm-svn: 247054
* Fix PR 24723 - Handle 0-mass backedges in irreducible loopsDiego Novillo2015-09-081-1/+4
| | | | | | | | | | | | This corner case happens when we have an irreducible SCC that is deeply nested. As we work down the tree, the backedge masses start getting smaller and smaller until we reach one that is down to 0. Since we distribute the incoming mass using the backedge masses as weight, the distributor does not allow zero weights. So, we simply ignore them (which will just use the weights of the non-zero nodes). llvm-svn: 247050
* [MC/ELF] Accept zero for .align directiveDavide Italiano2015-09-081-1/+5
| | | | | | | | | | .align directive refuses alignment 0 -- a comment in the code hints this is done for GNU as compatibility, but it seems GNU as accepts .align 0 (and silently rounds up alignment to 1). Differential Revision: http://reviews.llvm.org/D12682 llvm-svn: 247048
* Fix CPP Backend for GEP API changes for opaque pointer typesDavid Blaikie2015-09-081-15/+10
| | | | | | Based on a patch by Jerome Witmann. llvm-svn: 247047
* remove function names from comments; NFCSanjay Patel2015-09-081-49/+45
| | | | llvm-svn: 247043
* Fix for bz24500: Avoid non-deterministic code generation triggered by the ↵Andrew Kaylor2015-09-081-22/+25
| | | | | | | | | | x86 call frame optimization Patch by Dave Kreitzer Differential Revision: http://reviews.llvm.org/D12620 llvm-svn: 247042
* [libFuzzer] better documentatio for -save_minimized_corpus=1Kostya Serebryany2015-09-081-1/+2
| | | | llvm-svn: 247033
* [libFuzzer] remove -iterations as redundant (there is also -num_runs)Kostya Serebryany2015-09-084-7/+4
| | | | llvm-svn: 247030
* WebAssembly: NFC rename shr/sarJF Bastien2015-09-081-2/+2
| | | | | | Renamed from: https://github.com/WebAssembly/design/pull/332 llvm-svn: 247028
* [libFuzzer] add one more mutator: Mutate_ChangeASCIIIntegerKostya Serebryany2015-09-083-0/+67
| | | | llvm-svn: 247027
* Remove white space (test commit)Jun Bum Lim2015-09-081-1/+1
| | | | llvm-svn: 247021
* [mips][microMIPS] Implement LLE, LUI, LW and LWE instructionsZoran Jovanovic2015-09-083-1/+84
| | | | | | Differential Revision: http://reviews.llvm.org/D1179 llvm-svn: 247017
* AVX512: kunpck encoding implementation Igor Breger2015-09-082-17/+17
| | | | | | | | Added tests for encoding. Differential Revision: http://reviews.llvm.org/D12061 llvm-svn: 247010
* [WebAssembly] Enable SSA lowering and other pre-regalloc passesDan Gohman2015-09-081-1/+21
| | | | llvm-svn: 247008
* Removed an old comment, NFCElena Demikhovsky2015-09-081-2/+0
| | | | llvm-svn: 247006
* [mips][microMIPS] Implement SB, SBE, SCE, SH and SHE instructionsZoran Jovanovic2015-09-086-2/+109
| | | | | | Differential Revision: http://reviews.llvm.org/D11801 llvm-svn: 246999
* There is a trunc(lshr (zext A), Cst) optimization in InstCombineCasts thatJakub Kuderski2015-09-081-0/+20
| | | | | | | | | | | removes cast by performing the lshr on smaller types. However, currently there is no trunc(lshr (sext A), Cst) variant. This patch add such optimization by transforming trunc(lshr (sext A), Cst) to ashr A, Cst. Differential Revision: http://reviews.llvm.org/D12520 llvm-svn: 246997
* [mips] Reserve address spaces 1-255 for software use.Daniel Sanders2015-09-081-0/+8
| | | | | | | | | | | | Summary: And define them to have noop casts with address spaces 0-255. Reviewers: pekka.jaaskelainen Subscribers: pekka.jaaskelainen, llvm-commits Differential Revision: http://reviews.llvm.org/D12678 llvm-svn: 246990
* [mips][microMIPS] Add microMIPS32r6 and microMIPS64r6 tests for existing ↵Zoran Jovanovic2015-09-082-2/+4
| | | | | | | | 16-bit LBU16, LHU16, LW16, LWGP and LWSP instructions Differential Revision: http://reviews.llvm.org/D10956 llvm-svn: 246987
* compilation issue, NFCElena Demikhovsky2015-09-081-3/+3
| | | | llvm-svn: 246983
* fixed compilation issue, NFC.Elena Demikhovsky2015-09-081-3/+3
| | | | llvm-svn: 246982
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