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* Don't cast away constness.Benjamin Kramer2013-06-271-1/+2
| | | | llvm-svn: 185071
* [SystemZ] Allow LA and LARL to be rematerializedRichard Sandiford2013-06-271-2/+4
| | | | llvm-svn: 185069
* [SystemZ] Allow immediate moves to be rematerializedRichard Sandiford2013-06-271-2/+4
| | | | llvm-svn: 185068
* [SystemZ] Add conditional store patternsRichard Sandiford2013-06-277-9/+156
| | | | | | | | | | | | | | | | | | | | | Add pseudo conditional store instructions, so that we use: branch foo: store foo: instead of: load branch foo: move foo: store z196 has real 32-bit and 64-bit conditional stores, but we don't use any z196 instructions yet. llvm-svn: 185065
* Add a convenience createUniqueDirectory function.Rafael Espindola2013-06-271-0/+11
| | | | | | | | | | | There are a few valid situation where we care about the structure inside a directory, but not about the directory itself. A simple example is for unit testing directory traversal. PathV1 had a function like this, add one to V2 and port existing users of the created temp file and delete it hack to using it. llvm-svn: 185059
* LoopVectorize: Don't store a reversed value in the vectorized value mapArnold Schwaighofer2013-06-271-1/+4
| | | | | | | | | | When we store values for reversed induction stores we must not store the reversed value in the vectorized value map. Another instruction might use this value. This fixes 3 test cases of PR16455. llvm-svn: 185051
* Added support for the Builtin attribute.Michael Gottesman2013-06-279-16/+40
| | | | | | | | The Builtin attribute is an attribute that can be placed on function call site that signal that even though a function is declared as being a builtin, rdar://problem/13727199 llvm-svn: 185049
* No need to use a Set when a vector would do.Nadav Rotem2013-06-271-3/+3
| | | | llvm-svn: 185047
* SLP: When searching for vectorization opportunities scan the blocks in ↵Nadav Rotem2013-06-261-2/+4
| | | | | | post-order because we grow chains upwards. llvm-svn: 185041
* SLP: Dont erase instructions during vectorization because it prevents the ↵Nadav Rotem2013-06-261-2/+0
| | | | | | outerloops from iterating over the instructions. llvm-svn: 185040
* In InstCombine{AddSub,MulDivRem} convert APFloat.isFiniteNonZero() && ↵Michael Gottesman2013-06-262-5/+5
| | | | | | !APFloat.isDenormal => APFloat.isNormal. llvm-svn: 185037
* [APFloat] Convert all references to fcNormal to references to isFiniteNonZero().Michael Gottesman2013-06-261-30/+30
| | | | | | | | | | | | Currently inside APFloat fcNormal still implies the old definition of Normal (i.e. isFiniteNonZero) instead of the proper IEEE-754R definition that the external method isNormal() uses. This patch prepares for the internal switch inside APFloat by converting all references that check if a category is fcNormal directly with an indirect call via isFiniteNonZero(). llvm-svn: 185036
* Revert "Debug Info: clean up usage of Verify." as it's breaking bots.Eric Christopher2013-06-263-6/+6
| | | | | | This reverts commit r185020 llvm-svn: 185032
* Fix a crash bug in dumping options with groupsReid Kleckner2013-06-261-4/+6
| | | | | | | | Option groups don't have prefixes. Option dumping is basically dead code unless there is something wrong with the option table, so this isn't an important crasher. llvm-svn: 185031
* Clarify and doxygen-ify commentsStephen Lin2013-06-262-16/+20
| | | | llvm-svn: 185030
* [Mips Disassembler] Have the DecodeCCRRegisterClass function use the getRegChad Rosier2013-06-261-1/+4
| | | | | | | function to lookup the proper tablegen'ed register enumeration. Previously, it was using the encoded value directly. llvm-svn: 185026
* ARM: Proactively ensure that the LowerCallResult hack for 'this'-returns is ↵Stephen Lin2013-06-263-4/+23
| | | | | | | | not used for incompatible calling conventions. (Currently, ARM 'this'-returns are handled in the standard calling convention case by treating R0 as preserved and doing some extra magic in LowerCallResult; this may not apply to calling conventions added in the future so this patch provides and documents an interface for indicating such) llvm-svn: 185024
* Debug Info: clean up usage of Verify.Manman Ren2013-06-263-6/+6
| | | | | | | | No functionality change. It should suffice to check the type of a debug info metadata, instead of calling Verify. llvm-svn: 185020
* Minor formatting fix to ARMBaseRegisterInfo::getCalleeSavedRegsStephen Lin2013-06-261-7/+5
| | | | llvm-svn: 185016
* Rename PathV2 to just Path now that it is the only one.Rafael Espindola2013-06-264-11/+11
| | | | llvm-svn: 185015
* [mips] Do not emit ".option pic0" if target is mips64.Akira Hatanaka2013-06-261-1/+1
| | | | llvm-svn: 185012
* [mips] Improve code generation for constant multiplication using shifts, ↵Akira Hatanaka2013-06-261-0/+54
| | | | | | | | adds and subs. llvm-svn: 185011
* Use enums instead of raw octal values.Rafael Espindola2013-06-261-1/+0
| | | | | | Patch by 罗勇刚(Yonggang Luo). llvm-svn: 184971
* Erase all of the instructions that we RAUWedNadav Rotem2013-06-261-0/+9
| | | | llvm-svn: 184969
* Add a subtarget feature 'v8' to the ARM backend.Joey Gouly2013-06-268-4/+25
| | | | | | This allows for targeting the ARMv8 AArch32 variant. llvm-svn: 184967
* Do not add cse-ed instructions into the visited map because we dont want to ↵Nadav Rotem2013-06-261-5/+9
| | | | | | consider them as a candidate for replacement of instructions to be visited. llvm-svn: 184966
* ARM: fix more cases where predication may or may not be allowedTim Northover2013-06-264-36/+35
| | | | | | | | | | Unfortunately this addresses two issues (by the time I'd disentangled the logic it wasn't worth putting it back to half-broken): + Coprocessor instructions should all be predicable in Thumb mode. + BKPT should never be predicable. llvm-svn: 184965
* ARM: allow predicated barriers in Thumb modeTim Northover2013-06-262-18/+16
| | | | | | | The barrier instructions are only "always-execute" in ARM mode, they can quite happily sit inside an IT block in Thumb. llvm-svn: 184964
* Remove the 'generic' CPU from the ARM eabi attributes printer.Joey Gouly2013-06-261-9/+2
| | | | | | Make v4 the default ARM architecture attribute, to match CodeGen. llvm-svn: 184962
* PathV1 is deprecated since the 18th of Dec 2010. Remove it.Rafael Espindola2013-06-264-1164/+0
| | | | llvm-svn: 184960
* [PowerPC] Accept 17-bit signed immediates for addisUlrich Weigand2013-06-263-4/+26
| | | | | | | | | | | | | | | | | | | The assembler currently strictly verifies that immediates for s16imm operands are in range (-32768 ... 32767). This matches the behaviour of the GNU assembler, with one exception: gas allows, as a special case, operands in an extended range (-65536 .. 65535) for the addis instruction only (and its extended mnemonic lis). The main reason for this seems to be to allow using unsigned 16-bit operands for lis, e.g. like lis %r1, 0xfedc. Since this has been supported by gas for a long time, and assembler source code seen "in the wild" actually exploits this feature, this patch adds equivalent support to LLVM for compatibility reasons. llvm-svn: 184946
* [PowerPC] Support symbolic u16imm operandsUlrich Weigand2013-06-265-9/+14
| | | | | | | | | | | | | | Currently, all instructions taking s16imm operands support symbolic operands. However, for u16imm operands, we only support actual immediate integers. This causes the assembler to reject code like ori %r5, %r5, symbol@l This patch changes the u16imm operand definition to likewise accept symbolic operands. In fact, s16imm and u16imm can share the same encoding routine, now renamed to getImm16Encoding. llvm-svn: 184944
* ARM: operands should be explicit when disassembledAmaury de la Vieuville2013-06-261-8/+3
| | | | llvm-svn: 184943
* [Sparc]: Add memory operands for the frame references in the storeRegToStackSlotVenkatraman Govindaraju2013-06-261-8/+30
| | | | | | and loadRegFromStackSlot. llvm-svn: 184935
* Fixed a comment.Elena Demikhovsky2013-06-261-2/+2
| | | | llvm-svn: 184933
* Optimized integer vector multiplication operation by replacing it with ↵Elena Demikhovsky2013-06-262-22/+63
| | | | | | shift/xor/sub when it is possible. Fixed a bug in SDIV, where the const operand is not a splat constant vector. llvm-svn: 184931
* [asan] workaround for PR16277: don't instrument AllocaInstr with alignment ↵Kostya Serebryany2013-06-261-1/+2
| | | | | | more than the redzone size llvm-svn: 184928
* [asan] add option -asan-keep-uninstrumented-functionsKostya Serebryany2013-06-261-4/+47
| | | | llvm-svn: 184927
* Remove calls to Path in #ifdefs that don't seem to be used in any of the ↵Rafael Espindola2013-06-261-3/+3
| | | | | | bots :-( llvm-svn: 184920
* Fix the build when __APPLE__ is defined.Rafael Espindola2013-06-261-1/+5
| | | | llvm-svn: 184917
* Remove sys::GetMainExecutable.Rafael Espindola2013-06-262-116/+0
| | | | llvm-svn: 184916
* Port GetMainExecutable over to PathV2.Rafael Espindola2013-06-262-0/+113
| | | | | | I will remove the V1 version as soon as I change clang in the next commit. llvm-svn: 184914
* Remove PathWithStatus.Rafael Espindola2013-06-262-49/+0
| | | | llvm-svn: 184910
* dbgs() << Instruction doesn't print a newline on the end any more. Update theseNick Lewycky2013-06-261-5/+5
| | | | | | | debug statements to add a missing newline. Also canonicalize to '\n' instead of "\n"; the latter calls a function with a loop the former does not. llvm-svn: 184897
* s/C++0x/C++11/Adrian Prantl2013-06-251-1/+1
| | | | llvm-svn: 184892
* SLPVectorizer: support slp-vectorization of PHINodes between basic blocksNadav Rotem2013-06-251-1/+96
| | | | llvm-svn: 184888
* Print block frequencies in decimal form.Jakob Stoklund Olesen2013-06-251-1/+10
| | | | | | | | | This is easier to read than the internal fixed-point representation. If anybody knows the correct algorithm for converting fixed-point numbers to base 10, feel free to fix it. llvm-svn: 184881
* R600: Use new getNamedOperandIdx function generated by TableGenTom Stellard2013-06-2510-228/+160
| | | | llvm-svn: 184880
* X86 cost model: Vectorizing integer division is a bad ideaArnold Schwaighofer2013-06-251-0/+25
| | | | | | radar://14057959 llvm-svn: 184872
* Fix SROA to avoid unnecessary scalar conversions for 1-element vectors.Bob Wilson2013-06-251-15/+16
| | | | | | | | | | | When a 1-element vector alloca is promoted, a store instruction can often be rewritten without converting the value to a scalar and using an insertelement instruction to stuff it into the new alloca. This patch just adds a check to skip that conversion when it is unnecessary. This turns out to be really important for some ARM Neon operations where <1 x i64> is used to get around the fact that i64 is not a legal type. llvm-svn: 184870
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