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authorHal Finkel <hfinkel@anl.gov>2013-06-28 20:00:07 +0000
committerHal Finkel <hfinkel@anl.gov>2013-06-28 20:00:07 +0000
commit4ca70100de1c55bddd1ff9a2fb0347e2cb5a0520 (patch)
tree76559690166a2a8f8b2b2d4b40ae6355cb65fb38 /llvm/lib
parent95609be563f6581b8ca508983a3330ac017eb0c3 (diff)
downloadbcm5719-llvm-4ca70100de1c55bddd1ff9a2fb0347e2cb5a0520.tar.gz
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Fix a PPC rlwimi instruction-selection bug
Under certain (evidently rare) circumstances, this code used to convert OR(a, AND(x, y)) into OR(a, x). This was incorrect. While there, I've added a comment to the code immediately above. llvm-svn: 185201
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp4
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index 35f4b7c8d21..f8d990cee62 100644
--- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -447,10 +447,10 @@ SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) {
unsigned SHOpc = Op1.getOperand(0).getOpcode();
if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) &&
isInt32Immediate(Op1.getOperand(0).getOperand(1), Value)) {
+ // Note that Value must be in range here (less than 32) because
+ // otherwise there would not be any bits set in InsertMask.
Op1 = Op1.getOperand(0).getOperand(0);
SH = (SHOpc == ISD::SHL) ? Value : 32 - Value;
- } else {
- Op1 = Op1.getOperand(0);
}
}
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