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* RegAllocFast: Improve hinting heuristicMatt Arsenault2019-05-161-7/+84
| | | | | | | | | | | | | | | Trace through multiple COPYs when looking for a physreg source. Add hinting for vregs that will be copied into physregs (we only hinted for vregs getting copied to a physreg previously). Give hinted a register a bonus when deciding which value to spill. This is part of my rewrite regallocfast series. In fact this one doesn't even have an effect unless you also flip the allocation to happen from back to front of a basic block. Nonetheless it helps to split this up to ease review of D52010 Patch by Matthias Braun llvm-svn: 360887
* GlobalISel: Add DstOp version of buildIntrinsicMatt Arsenault2019-05-161-0/+12
| | | | llvm-svn: 360879
* Revert r360876 "[Object] Change object::SectionRef::getContents() to return ↵Hans Wennborg2019-05-1610-55/+37
| | | | | | | | | | | | Expected<StringRef>" It broke the Clang build, see llvm-commits thread. > Expected<ArrayRef<uint8_t>> may be better but use Expected<StringRef> for now. > > Follow-up of D61781. llvm-svn: 360878
* AMDGPU/GlobalISel: Correct regbank for 1-bit and/or/xorMatt Arsenault2019-05-161-1/+1
| | | | | | Bool values should use the scc/vcc regbank since r350611. llvm-svn: 360877
* [Object] Change object::SectionRef::getContents() to return Expected<StringRef>Fangrui Song2019-05-1610-37/+55
| | | | | | | | Expected<ArrayRef<uint8_t>> may be better but use Expected<StringRef> for now. Follow-up of D61781. llvm-svn: 360876
* [AArch64][SVE2] Asm: implement CMLA/SQRDCMLAH instructionsCullen Rhodes2019-05-162-0/+39
| | | | | | | | | | | | | | | Summary: This patch adds support for the indexed and unpredicated vectors forms of the CMLA and SQRDCMLAH instructions. The specification can be found here: https://developer.arm.com/docs/ddi0602/latest Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D61906 llvm-svn: 360871
* [AArch64][SVE2] Asm: implement CDOT instructionCullen Rhodes2019-05-162-0/+79
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: The complex DOT instructions perform a dot-product on quadtuplets from two source vectors and the resuling wide real or wide imaginary is accumulated into the destination register. The instructions come in two forms: Vector form, e.g. cdot z0.s, z1.b, z2.b, #90 - complex dot product on four 8-bit quad-tuplets, accumulating results in 32-bit elements. The complex numbers in the second source vector are rotated by 90 degrees. cdot z0.d, z1.h, z2.h, #180 - complex dot product on four 16-bit quad-tuplets, accumulating results in 64-bit elements. The complex numbers in the second source vector are rotated by 180 degrees. Indexed form, e.g. cdot z0.s, z1.b, z2.b[3], #0 - complex dot product on four 8-bit quad-tuplets, with specified quadtuplet from second source vector, accumulating results in 32-bit elements. cdot z0.d, z1.h, z2.h[1], #0 - complex dot product on four 16-bit quad-tuplets, with specified quadtuplet from second source vector, accumulating results in 64-bit elements. The specification can be found here: https://developer.arm.com/docs/ddi0602/latest Reviewed By: SjoerdMeijer, rovka Differential Revision: https://reviews.llvm.org/D61903 llvm-svn: 360870
* [AArch64][SVE2] Asm: add unpredicated integer multiply instructionsCullen Rhodes2019-05-162-0/+86
| | | | | | | | | | | | | | | | | | | | | Summary: Add support for the following instructions: * MUL (indexed and unpredicated vectors forms) * SQDMULH (indexed and unpredicated vectors forms) * SQRDMULH (indexed and unpredicated vectors forms) * SMULH (unpredicated, predicated form added in SVE) * UMULH (unpredicated, predicated form added in SVE) * PMUL (unpredicated) The specification can be found here: https://developer.arm.com/docs/ddi0602/latest Reviewed By: SjoerdMeijer, rovka Differential Revision: https://reviews.llvm.org/D61902 llvm-svn: 360867
* Add Triple::isPPC64()Fangrui Song2019-05-163-5/+4
| | | | llvm-svn: 360864
* Reland r360771 "[MergeICmps] Simplify the code."Clement Courbet2019-05-161-145/+150
| | | | | | This revision does not seem to be the culprit. llvm-svn: 360859
* [IRMover] Improve diagnostic messages for conflicting metadataIgor Kudrin2019-05-161-3/+9
| | | | | | | | | | | | This does the similar for error messages as rL344011 has done for warnings. With llvm::lto::LTO, the error might appear when LTO::run() is executed. In that case, the calling code cannot know which module causes the error and, subsequently, cannot hint the user. Differential Revision: https://reviews.llvm.org/D61880 llvm-svn: 360857
* GlobalISel: Add buildFConstant for APFloatMatt Arsenault2019-05-161-0/+7
| | | | llvm-svn: 360853
* GlobalISel: Fix indentationMatt Arsenault2019-05-161-1/+1
| | | | llvm-svn: 360851
* GlobalISel: Add G_FCOPYSIGNMatt Arsenault2019-05-161-0/+2
| | | | llvm-svn: 360850
* [JITLink][MachO] Use getSymbol64TableEntry for 64-bit MachO files.Lang Hames2019-05-161-1/+1
| | | | | | | Fixes a think-o. No test case: The nlist and nlist64 data structures happen to line up for this field, so there's no way to construct a failing test case. llvm-svn: 360830
* [X86] Delay creating index register negations during address matching until ↵Craig Topper2019-05-151-7/+15
| | | | | | | | | | after we know for sure the match will succeed If we're trying to match an LEA, its possible the LEA match will be deemed unprofitable. In which case the negation we created in matchAddress would be left dangling in the SelectionDAG. This could artificially increase use counts for other nodes in the DAG. Though I don't have an example of that. But it just seems like bad form to have dangling nodes in isel. Differential Revision: https://reviews.llvm.org/D61047 llvm-svn: 360823
* [codeview] Fix SDNode representation of annotation labelsReid Kleckner2019-05-153-1/+4
| | | | | | | | | | | Before this change, they were erroneously constructed with the EH_LABEL SDNode opcode, which caused other passes to interact with them in incorrect ways. See the FIXME about fastisel that this addresses in the existing test case. Fixes PR41890 llvm-svn: 360818
* [mips] Use range-based `for` loops. NFCSimon Atanasyan2019-05-151-20/+17
| | | | llvm-svn: 360817
* [AArch64] only indicate CFI on Windows if we emitted CFIMandeep Singh Grang2019-05-153-37/+80
| | | | | | | | | | | | | | | | | | | | | | | Summary: Otherwise, we emit directives for CFI without any actual CFI opcodes to go with them, which causes tools to malfunction. The technique is similar to what the x86 backend already does. Fixes https://bugs.llvm.org/show_bug.cgi?id=40876 Patch by: froydnj (Nathan Froyd) Reviewers: mstorsjo, eli.friedman, rnk, mgrang, ssijaric Reviewed By: rnk Subscribers: javed.absar, kristof.beyls, llvm-commits, dmajor Tags: #llvm Differential Revision: https://reviews.llvm.org/D61960 llvm-svn: 360816
* [X86] Strengthen type constraints on some specialized X86 ISD opcodes that ↵Craig Topper2019-05-151-5/+17
| | | | | | | | | | | | don't have any flexibility. NFC These particular instructions only operate on 128-bit vectors and have no wider equivalents. And the element size is always known. One could argue that MOVSS/MOVSD could be merged, but that's probably disruptive to code in X86ISelLowering and probably low value. llvm-svn: 360815
* [codeview] Finish support for reading and writing S_ANNOTATION recordsReid Kleckner2019-05-153-0/+30
| | | | | | Implement dumping via llvm-pdbutil and llvm-readobj. llvm-svn: 360813
* Uncomment LLVM_FALLTHROUGH.Pete Couperus2019-05-151-1/+1
| | | | llvm-svn: 360798
* [PredicateInfo] Do not process unreachable operands.Taewook Oh2019-05-151-1/+2
| | | | | | | | | | | | | | Summary: We should excluded unreachable operands from processing as their DFS visitation order is undefined. When `renameUses` function sorts `OpsToRename` (https://fburl.com/d2wubn60), the comparator assumes that the parent block of the operand has a corresponding dominator tree node. This is not the case for unreachable operands and crashes the compiler. Reviewers: dberlin, mgrang, davide Subscribers: efriedma, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D61154 llvm-svn: 360796
* [MachineOperand] Add a ChangeToGA methodNicolai Haehnle2019-05-151-0/+13
| | | | | | | | | | | | | | | | | | Summary: Analogous to the other ChangeToXXX methods. See the next patch for a use case. Change-Id: I6548d614706834fb9109ab3c8fe915e9c6ece2a7 Reviewers: arsenm, kzhuravl Subscribers: wdng, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D61651 llvm-svn: 360789
* RegAlloc: try to fail more gracefully when out of registersNicolai Haehnle2019-05-151-6/+10
| | | | | | | | | | | | | | | | | | | | | | | Summary: The emitError path allows the program to continue, unlike report_fatal_error. This is friendlier to use cases where LLVM is embedded in a larger program, because the caller may be able to deal with the error somewhat gracefully. Change the number of requested NOP bytes in the AArch64 and PowerPC test cases to avoid triggering an unrelated assertion. The compilation still fails, as verified by the test. Change-Id: Iafb9ca341002a597b82e59ddc7a1f13c78758e3d Reviewers: arsenm, MatzeB Subscribers: qcolombet, nemanjai, wdng, javed.absar, kristof.beyls, kbarton, jsji, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D61489 llvm-svn: 360786
* [JumpThreading] A bug fix for stale loop info after unfold selectHiroshi Yamauchi2019-05-151-1/+2
| | | | | | | | | | | | | | | | | | | | Summary: The return value of a TryToUnfoldSelect call was not checked, which led to an incorrectly preserved loop info and some crash. The original crash was reported on https://reviews.llvm.org/D59514. Reviewers: davidxl, amehsan Reviewed By: davidxl Subscribers: fhahn, brzycki, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D61920 llvm-svn: 360780
* [AMDGPU] Increases available SGPR for Calling ConventionRyan Taylor2019-05-152-4/+22
| | | | | | | | | | | | | | | | Summary: SGPR in CC can be either hw initialized or set by other chained shaders and so this increases the SGPR count availalbe to CC to 105. Change-Id: I3dfadc750fe4a3e2bd07117a2899fd13f3e2fef3 Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D61261 llvm-svn: 360778
* Teach InstSimplify -X + X --> 0.0 about unary FNegCameron McInally2019-05-151-4/+10
| | | | | | Differential Revision: https://reviews.llvm.org/D61916 llvm-svn: 360777
* Revert r360771 "[MergeICmps] Simplify the code."Clement Courbet2019-05-151-150/+145
| | | | | | Breaks a bunch of builbdots. llvm-svn: 360776
* [MergeICmps] Fix r360771.Clement Courbet2019-05-151-5/+5
| | | | | | Twine references a StringRef by reference, not value... llvm-svn: 360775
* Revert "[Salvage] Change salvage debug info implementation to use ↵Stephen Tozer2019-05-151-21/+2
| | | | | | | | | DW_OP_LLVM_convert where needed" This reverts r360772 due to build issues. Reverted commit: 17dd4d7403770bd683675e45f5517e0cdb8f9b2b. llvm-svn: 360773
* [Salvage] Change salvage debug info implementation to use DW_OP_LLVM_convert ↵Stephen Tozer2019-05-151-2/+21
| | | | | | | | | | | | | | | | | | where needed Fixes issue: https://bugs.llvm.org/show_bug.cgi?id=40645 Previously, LLVM had no functional way of performing casts inside of a DIExpression(), which made salvaging cast instructions other than Noop casts impossible. With the recent addition of DW_OP_LLVM_convert this salvaging is now possible, and so can be used to fix the attached bug as well as any cases where SExt instruction results are lost in the debugging metadata. This patch introduces this fix by expanding the salvage debug info method to cover these cases using the new operator. Differential revision: https://reviews.llvm.org/D61184 llvm-svn: 360772
* [MergeICmps] Simplify the code.Clement Courbet2019-05-151-145/+150
| | | | | | | | | | | | | | | | | | | Instead of patching the original blocks, we now generate new blocks and delete the old blocks. This results in simpler code with a less twisted control flow (see the change in `entry-block-shuffled.ll`). This will make https://reviews.llvm.org/D60318 simpler by making it more obvious where control flow created and deleted. Reviewers: gchatelet Subscribers: hiraditya, llvm-commits, spatel Tags: #llvm Differential Revision: https://reviews.llvm.org/D61736 llvm-svn: 360771
* Revert rL360675 : [APFloat] APFloat::Storage::Storage - fix use after moveSimon Pilgrim2019-05-151-3/+3
| | | | | | | | This was mentioned both in https://www.viva64.com/en/b/0629/ and by scan-build checks ........ There's concerns this may just introduce a use-after-free instead..... llvm-svn: 360770
* [ARM] Don't use the Machine Scheduler for cortex-m at minsizeDavid Green2019-05-152-1/+8
| | | | | | | | | | | | | | | | | | The new cortex-m schedule in rL360768 helps performance, but can increase the amount of high-registers used. This, on average, ends up increasing the codesize by a fair amount (because less instructions are converted from T2 to T1). On cortex-m at -Oz, where we are quite size-paranoid, it is better to use the existing DAG scheduler with the RegPressure scheduling preference (at least until the issues around T2 vs T1 instructions can be improved). I have also made sure that the Sched::RegPressure dag scheduler is always chosen for MinSize. The test shows one case where we increase the number of registers used. Differential Revision: https://reviews.llvm.org/D61882 llvm-svn: 360769
* [ARM] Cortex-M4 scheduleDavid Green2019-05-156-65/+176
| | | | | | | | | | | | | | | | | | | | This patch adds a simple Cortex-M4 schedule, renaming the existing M3 schedule to M4 and filling in the latencies as-per the Cortex-M4 TRM: https://developer.arm.com/docs/ddi0439/latest Most of these are 1, with the important exception being loads taking 2 cycles. A few others are also higher, but I don't believe they make a large difference. I've repurposed the M3 schedule as the latencies are mostly the same between the two cores, with the M4 having more FP and DSP instructions. We also turn on MISched and UseAA for the cores that now use this. It also adds some schedule Write's to various instruction to make things simpler. Differential Revision: https://reviews.llvm.org/D54142 llvm-svn: 360768
* [mips] LLVM and GAS now use same instructions for CFA Definition. NFCISimon Atanasyan2019-05-151-1/+1
| | | | | | | | | | | | | LLVM previously used `DW_CFA_def_cfa` instruction in .eh_frame to set the register and offset for current CFA rule. We change it to `DW_CFA_def_cfa_register` which is the same one used by GAS that only changes the register but keeping the old offset. Patch by Mirko Brkusanin. Differential Revision: https://reviews.llvm.org/D61899 llvm-svn: 360765
* [LV] Move getScalarizationOverhead and vector call cost computations to CM. ↵Florian Hahn2019-05-152-62/+61
| | | | | | | | | | | | | | | | | | | | | (NFC) This reduces the number of parameters we need to pass in and they seem a natural fit in LoopVectorizationCostModel. Also simplifies things for D59995. As a follow up refactoring, we could only expose a expose a shouldUseVectorIntrinsic() helper in LoopVectorizationCostModel, instead of calling getVectorCallCost/getVectorIntrinsicCost in InnerLoopVectorizer/VPRecipeBuilder. Reviewers: Ayal, hsaito, dcaballe, rengolin Reviewed By: rengolin Differential Revision: https://reviews.llvm.org/D61638 llvm-svn: 360758
* [[DAGCombiner][NFC] Add a comment.Clement Courbet2019-05-151-0/+2
| | | | | | As suggested in D61846. llvm-svn: 360755
* [X86] Use OR32mi8Locked instead of LOCK_OR32mi8 in emitLockedStackOp.Craig Topper2019-05-152-5/+3
| | | | | | | | | | | They encode the same way, but OR32mi8Locked sets hasUnmodeledSideEffects set which should be stronger than the mayLoad/mayStore on LOCK_OR32mi8. I think this makes sense since we are using it as a fence. This also seems to hide the operation from the speculative load hardening pass so I've reverted r360511. llvm-svn: 360747
* [IR] Disallow llvm.global_ctors and llvm.global_dtors of the 2-field form in ↵Fangrui Song2019-05-155-46/+56
| | | | | | | | | | | | | | | | | | | | textual format The 3-field form was introduced by D3499 in 2014 and the legacy 2-field form was planned to be removed in LLVM 4.0 For the textual format, this patch migrates the existing 2-field form to use the 3-field form and deletes the compatibility code. test/Verifier/global-ctors-2.ll checks we have a friendly error message. For bitcode, lib/IR/AutoUpgrade UpgradeGlobalVariables will upgrade the 2-field form (add i8* null as the third field). Reviewed By: rnk, dexonsmith Differential Revision: https://reviews.llvm.org/D61547 llvm-svn: 360742
* [NFC] Reuse a helper function to eliminate duplicate codePhilip Reames2019-05-151-79/+67
| | | | llvm-svn: 360740
* [XCore] Create a TargetInfo header. NFCRichard Trieu2019-05-157-8/+25
| | | | | | | | Move the declarations of getThe<Name>Target() functions into a new header in TargetInfo and make users of these functions include this new header. This fixes a layering problem. llvm-svn: 360738
* [X86] Create a TargetInfo header. NFCRichard Trieu2019-05-158-4/+27
| | | | | | | | Move the declarations of getThe<Name>Target() functions into a new header in TargetInfo and make users of these functions include this new header. This fixes a layering problem. llvm-svn: 360736
* [WebAssembly] Create a TargetInfo header. NFCRichard Trieu2019-05-158-5/+32
| | | | | | | | Move the declarations of getThe<Name>Target() functions into a new header in TargetInfo and make users of these functions include this new header. This fixes a layering problem. llvm-svn: 360735
* [SystemZ] Create a TargetInfo header. NFCRichard Trieu2019-05-158-3/+26
| | | | | | | | Move the declarations of getThe<Name>Target() functions into a new header in TargetInfo and make users of these functions include this new header. This fixes a layering problem. llvm-svn: 360734
* [Sparc] Create a TargetInfo header. NFCRichard Trieu2019-05-158-12/+28
| | | | | | | | Move the declarations of getThe<Name>Target() functions into a new header in TargetInfo and make users of these functions include this new header. This fixes a layering problem. llvm-svn: 360733
* [RISCV] Create a TargetInfo header. NFCRichard Trieu2019-05-158-7/+29
| | | | | | | | Move the declarations of getThe<Name>Target() functions into a new header in TargetInfo and make users of these functions include this new header. This fixes a layering problem. llvm-svn: 360732
* [PowerPC] Create a TargetInfo header. NFCRichard Trieu2019-05-158-6/+28
| | | | | | | | Move the declarations of getThe<Name>Target() functions into a new header in TargetInfo and make users of these functions include this new header. This fixes a layering problem. llvm-svn: 360731
* [NVPTX] Create a TargetInfo header. NFCRichard Trieu2019-05-147-8/+25
| | | | | | | | Move the declarations of getThe<Name>Target() functions into a new header in TargetInfo and make users of these functions include this new header. This fixes a layering problem. llvm-svn: 360729
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