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* Use std::unique_ptr to make the ownership explicit.Rafael Espindola2014-07-3110-19/+24
| | | | llvm-svn: 214377
* Don't fail tablegen immediately after failing to set a value.Pete Cooper2014-07-311-1/+4
| | | | | | | | Instead allow the variable to be declared, but don't attach an initializer. This allows more than a single error to be emitted before we exit. Test case to follow soon in another patch. llvm-svn: 214375
* Add a better error message when failing to assign one tablegen value to anotherPete Cooper2014-07-311-1/+8
| | | | | | | | This is currently for assigning from one bit init to another. It can easily be extended to other types. Test to follow soon in another patch. llvm-svn: 214374
* Fix bit initializer which was one bit too long, but worked so long as we ↵Pete Cooper2014-07-311-1/+1
| | | | | | silently dropped the leading 0 llvm-svn: 214373
* Fix bit initializer which was one bit too long, but worked so long as we ↵Pete Cooper2014-07-311-1/+1
| | | | | | silently dropped the leading 0 llvm-svn: 214372
* Delete dead code.Rafael Espindola2014-07-313-10/+4
| | | | llvm-svn: 214370
* UseListOrder: Don't give constant IDs to GlobalValuesDuncan P. N. Exon Smith2014-07-311-3/+6
| | | | | | | | | | | Since initializers of GlobalValues are being assigned IDs before GlobalValues themselves, explicitly exclude GlobalValues from the constant pool. Added targeted test in `test/Bitcode/use-list-order.ll` and added two more RUN lines in `test/Assembly`. This is part of PR5680. llvm-svn: 214368
* [FastISel] Fix the patchpoint intrinsic lowering in FastISel for large ↵Juergen Ributzka2014-07-311-1/+1
| | | | | | | | | target addresses. This fixes a mistake where I accidentially dropped the upper 32bit of a 64bit pointer during FastISel lowering of the patchpoint intrinsic. llvm-svn: 214367
* [FastISel][AArch64 and X86] Don't emit stores for UNDEF arguments during ↵Juergen Ributzka2014-07-312-0/+9
| | | | | | | | | | function call lowering. UNDEF arguments are not ment to be touched - especially for the webkit_js calling convention. This fix reproduces the already existing behavior of SelectionDAG in FastISel. llvm-svn: 214366
* X86 asm parser: Avoid duplicating the list of aliased instructionsReid Kleckner2014-07-311-16/+11
| | | | | | No functional change. llvm-svn: 214364
* Add mtpid/mfpid for BookE.Joerg Sonnenberger2014-07-301-0/+3
| | | | llvm-svn: 214363
* Attempt at fixing the windows dll build.Rafael Espindola2014-07-301-1/+1
| | | | | | | It looks like only direct (i.e., explicitly listed) dependencies are scanned. llvm-svn: 214361
* Use "weak alias" instead of "alias weak"Rafael Espindola2014-07-303-18/+14
| | | | | | | | | | | | | | | | | | | | | Before this patch we had @a = weak global ... but @b = alias weak ... The patch changes aliases to look more like global variables. Looking at some really old code suggests that the reason was that the old bison based parser had a reduction for alias linkages and another one for global variable linkages. Putting the alias first avoided the reduce/reduce conflict. The days of the old .ll parser are long gone. The new one parses just "linkage" and a later check is responsible for deciding if a linkage is valid in a given context. llvm-svn: 214355
* Refactor TLBIVAX and add tlbsx.Joerg Sonnenberger2014-07-302-8/+10
| | | | llvm-svn: 214354
* X86 asm parser: Use a loop to disambiguate suffixes instead of copy pasteReid Kleckner2014-07-301-38/+20
| | | | | | | | | This works towards making the Intel syntax asm matcher use a completely different disambiguation strategy. No functional change. llvm-svn: 214352
* [FastISel][AArch64] Add select folding support for the XALU intrinsics.Juergen Ributzka2014-07-301-34/+36
| | | | | | | | | | | This improves the code generation for the XALU intrinsics when the condition is feeding a select instruction. This also updates and enables the XALU unit tests for FastISel. This fixes <rdar://problem/17831117>. llvm-svn: 214350
* [FastISel][AArch64] Add branch folding support for the XALU intrinsics.Juergen Ributzka2014-07-301-3/+77
| | | | | | | | | This improves the code generation for the XALU intrinsics when the condition is feeding a branch instruction. This is related to <rdar://problem/17831117>. llvm-svn: 214349
* [FastISel][AArch64] Add {s|u}{add|sub|mul}.with.overflow intrinsic support.Juergen Ributzka2014-07-301-0/+171
| | | | | | | | | | This commit adds support for the {s|u}{add|sub|mul}.with.overflow intrinsics. The unit tests for FastISel will be enabled in a later commit, once there is also branch and select folding support. This is related to <rdar://problem/17831117>. llvm-svn: 214348
* [FastISel] Move the helper function isCommutativeIntrinsic into FastISel ↵Juergen Ributzka2014-07-301-12/+0
| | | | | | | | | base class. Move the helper function isCommutativeIntrinsic into the FastISel base class, so it can be used by more than just one backend. llvm-svn: 214347
* [FastISel][AArch64] Create helper functions to create the various multiplies ↵Juergen Ributzka2014-07-301-24/+70
| | | | | | on AArch64. llvm-svn: 214346
* [FastISel][AArch64] Add support for shift-immediate.Juergen Ributzka2014-07-301-1/+101
| | | | | | | | Currently the shift-immediate versions are not supported by tblgen and hopefully this can be later removed, once the required support has been added to tblgen. llvm-svn: 214345
* InstCombine: Simplify (A ^ B) or/and (A ^ B ^ C)David Majnemer2014-07-301-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While we can already transform A | (A ^ B) into A | B, things get bad once we have (A ^ B) | (A ^ B ^ Cst) because reassociation will morph this into (A ^ B) | ((A ^ Cst) ^ B). Our existing patterns fail once this happens. To fix this, we add a new pattern which looks through the tree of xor binary operators to see that, in fact, there exists a redundant xor operation. What follows bellow is a correctness proof of the transform using CVC3. $ cat t.cvc A, B, C : BITVECTOR(64); QUERY BVXOR(A, B) | BVXOR(BVXOR(B, C), A) = BVXOR(A, B) | C; QUERY BVXOR(BVXOR(A, C), B) | BVXOR(A, B) = BVXOR(A, B) | C; QUERY BVXOR(A, B) & BVXOR(BVXOR(B, C), A) = BVXOR(A, B) & ~C; QUERY BVXOR(BVXOR(A, C), B) & BVXOR(A, B) = BVXOR(A, B) & ~C; $ cvc3 < t.cvc Valid. Valid. Valid. Valid. llvm-svn: 214342
* Add rfdi and rfmci from the e500/e500mc ISA.Joerg Sonnenberger2014-07-301-0/+3
| | | | llvm-svn: 214339
* SLP Vectorizer: Canonicalize tree operands of commutitive binary operands.Chad Rosier2014-07-301-12/+32
| | | | llvm-svn: 214338
* SimplifyCFG: Avoid miscompilations due to removed lifetime intrinsics.Rafael Espindola2014-07-301-1/+1
| | | | | | | | | | | The lifetime intrinsics need some work in order to make it clear which optimizations are or are not valid. For now dropping this optimization avoids a miscompilation. Patch by Björn Steinbrink. llvm-svn: 214336
* Add BookE's tlbre, tlbwe and tlbivax instructions.Joerg Sonnenberger2014-07-301-0/+15
| | | | llvm-svn: 214332
* Refactor duplicated code.Rafael Espindola2014-07-303-47/+31
| | | | llvm-svn: 214328
* Fixing a few -Woverloaded-virtual warnings by exposing the hidden virtual ↵Aaron Ballman2014-07-302-0/+4
| | | | | | function as well. No functional changes intended. llvm-svn: 214325
* Retain alignment requirements for load->selects modified by DAGCombineLouis Gerbarg2014-07-301-2/+6
| | | | | | | | | | | | | | | | | DAGCombine may choose to rewrite graphs where two loads feed a select into graphs where a select of two addresses feed a load. While it sanity checks the loads to make sure they are broadly equivalent it currently just uses the alignment restriction of the left node. In cases where the right node has stronger alignment requiresment this may lead to bad codegen, such as generating an aligned load where an unaligned load is required. This patch makes the combine generate a load with an alignment that is the same as whichever is more restrictive of the two alignments. Tests included. rdar://17762530 llvm-svn: 214322
* UseListOrder: Visit global valuesDuncan P. N. Exon Smith2014-07-301-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When predicting use-list order, we visit functions in reverse order followed by `GlobalValue`s and write out use-lists at the first opportunity. In the reader, this will translate to *after* the last use has been added. For this to work, we actually need to descend into `GlobalValue`s. Added a targeted test in `use-list-order.ll` and `RUN` lines to the newly passing tests in `test/Bitcode`. There are two remaining failures in `test/Bitcode`: - blockaddress.ll: I haven't thought through how to model the way block addresses change the order of use-lists (or how to work around it). - metadata-2.ll: There's an old-style `@llvm.used` global array here that I suspect the .ll parser isn't upgrading properly. When it round-trips through bitcode, the .bc reader *does* upgrade it, so the extra variable (`i8* null`) has an extra use, and the shuffle vector doesn't match. I think the fix is to upgrade old-style global arrays (or reject them?) in the .ll parser. This is part of PR5680. llvm-svn: 214321
* Add the missing hasLinkOnceODRLinkage predicate.Rafael Espindola2014-07-303-7/+3
| | | | llvm-svn: 214312
* Add BookE's wrtee and wrteei instructions.Joerg Sonnenberger2014-07-301-0/+13
| | | | llvm-svn: 214297
* SPRG 0 to 3 are valid outside BookE, so move them to the normal testJoerg Sonnenberger2014-07-302-0/+20
| | | | | | file. Add support for accessing SPRG 4 to 7 on BookE. llvm-svn: 214295
* Don't manually (and forcibly) run the verifier on the entire module fromChandler Carruth2014-07-301-4/+0
| | | | | | | | | | | | | the jump instruction table pass. First, the verifier is already built into all the tools. The test case is adapted to just run llvm-as demonstrating that we still catch the broken module. Second, the verifier is *extremely* slow. This was responsible for very significant compile time regressions. If you have deployed a Clang binary anywhere from r210280 to this commit, you really want to re-deploy. llvm-svn: 214287
* [MCJIT] Fix the ARM BR24 relocation in RuntimeDyldMachO.Lang Hames2014-07-306-12/+31
| | | | | | | | | | We now (1) correctly decode the branch immediate, (2) modify the immediate to corretly treat it as PC-rel, and (3) properly populate the stub entry. Previously we had been doing each of these wrong. <rdar://problem/17750739> llvm-svn: 214285
* R600/SI: Remove redundant setting of bits on instructions.Matt Arsenault2014-07-301-13/+2
| | | | | | | | neverHasSideEffects is deprecated, and hasSideEffects = 0 is already set on the base classes of the basic ALU instruction classes. The base classes also already set mayLoad = 0 and mayStore = 0 llvm-svn: 214283
* Reapply "UseListOrder: Order GlobalValue uses after initializers"Duncan P. N. Exon Smith2014-07-301-14/+55
| | | | | | | This reverts commit r214249, reapplying r214242 and r214243, now that r214270 has fixed the UB. llvm-svn: 214271
* UseListOrder: Fix undefined behaviourDuncan P. N. Exon Smith2014-07-301-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | This commit fixes undefined behaviour that caused the revert in r214249. The problem was two unsequenced operations on a `DenseMap<>`, giving different behaviour in GCC and Clang. This: DenseMap<T*, unsigned> DM; for (auto &X : ...) DM[&X] = DM.size() + 1; should have been: DenseMap<T*, unsigned> DM; for (auto &X : ...) { unsigned Size = DM.size(); DM[&X] = Size + 1; } Until r214242, this difference between compilers didn't matter. In r214242, `OrderMap::LastGlobalValueID` was introduced and compared against IDs, which in GCC were off-by-one my expectations. llvm-svn: 214270
* R600/SI: Consider adjacent offsets in getLdStBaseRegImmOfsMatt Arsenault2014-07-301-13/+39
| | | | | | | | | We can treat ds_read2_* as a single offset if the offsets are adjacent. No test since emission of read2 instructions for partially aligned loads isn't implemented yet. llvm-svn: 214269
* Add support for scalarizing ctlz_zero_undefPetar Jovanovic2014-07-301-0/+1
| | | | | | | | | Fix the missing case in ScalarizeVectorResult() that was exposed with libclcore.bc in Android. Differential Revision: http://reviews.llvm.org/D4645 llvm-svn: 214266
* Header hygiene: remove using directive and #undef DEBUG_TYPE once we're done.Richard Smith2014-07-301-0/+2
| | | | llvm-svn: 214263
* Add rfci instruction.Joerg Sonnenberger2014-07-291-1/+4
| | | | llvm-svn: 214256
* [MCJIT] Add options to llvm-rtdyld to describe a phony target address space forLang Hames2014-07-291-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | use in -verify mode. This patch adds three hidden command line options to llvm-rtdyld: -target-addr-start <start-addr> : Specify the start of the virtual address space on the phony target. -target-addr-end <end-addr> : Specify the end of the virtual address space on the phony target. -target-section-sep <sep> : Specify the separation (in bytes) between the end of one section and the start of the next. These options automatically default to sane values for the target platform. In particular, they allow narrow (e.g. 32-bit, 16-bit) targets to be tested from wider (e.g. 64-bit, 32-bit) hosts without overflowing pointers. The section separation option defaults to zero, but can be set to a large number (e.g. 1 << 32) to force large separations between sections in order to stress-test large-code-model code. llvm-svn: 214255
* mbar without argument is equivalent to mbar 0.Joerg Sonnenberger2014-07-291-0/+2
| | | | llvm-svn: 214250
* Revert "UseListOrder: Order GlobalValue uses after initializers"Duncan P. N. Exon Smith2014-07-291-55/+14
| | | | | | | | | | | | This reverts commits r214242 and r214243 while I investigate buildbot failures [1][2][3]. I can't reproduce these failures locally, so if anyone can see what I've done wrong, I'd appreciate a note. [1]: http://lab.llvm.org:8011/builders/llvm-hexagon-elf/builds/9840 [2]: http://lab.llvm.org:8011/builders/clang-hexagon-elf/builds/14981 [3]: http://bb.pgr.jp/builders/cmake-llvm-x86_64-linux/builds/15191 llvm-svn: 214249
* Recognize BookE's mbar instruction.Joerg Sonnenberger2014-07-292-0/+12
| | | | llvm-svn: 214244
* UseListOrder: Order GlobalValue uses after initializersDuncan P. N. Exon Smith2014-07-291-14/+55
| | | | | | | | | | | | To avoid unnecessary forward references, the reader doesn't process initializers of `GlobalValue`s until after the constant pool has been processed, and then in reverse order. Model this when predicting use-list order. This gets two more Bitcode tests passing with `llvm-uselistorder`. Part of PR5680. llvm-svn: 214242
* UseListOrder: Create a struct around OrderMap, NFCDuncan P. N. Exon Smith2014-07-291-1/+9
| | | | llvm-svn: 214241
* Feedback on r214189, no functionality change.Manman Ren2014-07-293-3/+3
| | | | llvm-svn: 214240
* Fix typo in alias: DSIR -> DSISRJoerg Sonnenberger2014-07-291-2/+2
| | | | llvm-svn: 214238
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