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* [PPC] Change i32 constant in store instruction to i64Guozhi Wei2017-11-161-1/+16
| | | | | | | | This patch changes all i32 constant in store instruction to i64 with truncation, to increase the chance that the referenced constant can be shared with other i64 constant. Differential Revision: https://reviews.llvm.org/D39352 llvm-svn: 318436
* Add ELF dynamic symbol support to yaml2obj/obj2yamlDave Lee2017-11-161-0/+1
| | | | | | | | | | | | | | | | | | Summary: This change introduces a `DynamicSymbols` field to the ELF specific YAML supported by `yaml2obj` and `obj2yaml`. This grouping of symbols provides a way to represent ELF dynamic symbols. The `DynamicSymbols` structure is identical to the existing `Symbols`. Reviewers: compnerd, jakehehrlich, silvas Reviewed By: silvas Subscribers: silvas, jakehehrlich, llvm-commits Differential Revision: https://reviews.llvm.org/D39582 llvm-svn: 318433
* Allow empty mappings for optional YAML inputDave Lee2017-11-161-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This change fixes a bug where `obj2yaml` can in some cases produce YAML that causes `yaml2obj` to error. The ELF YAML document structure has a `Sections` mapping, which contains three mappings, all of which are optional: `Local`, `Global`, and `Weak.` Any one of these can be missing, but if all three are missing, then `yaml2obj` errors. This change allows YAML input for cases like this one. I have tested this with check-llvm and check-lld, and all tests passed. This change is the result of test failures while working on D39582, which introduces a `DynamicSymbols` mapping, which will be empty at times. Reviewers: compnerd, jakehehrlich, silvas, kledzik, mehdi_amini, pcc Reviewed By: compnerd Subscribers: silvas, llvm-commits Differential Revision: https://reviews.llvm.org/D39908 llvm-svn: 318428
* [asan] Fix small X86_64 ShadowOffset for non-default shadow scaleWalter Lee2017-11-161-7/+9
| | | | | | | | | | The requirement is that shadow memory must be aligned to page boundaries (4k in this case). Use a closed form equation that always satisfies this requirement. Differential Revision: https://reviews.llvm.org/D39471 llvm-svn: 318421
* Revert "[Support][CachePruning] Fix regression in pruning interval"Rafael Espindola2017-11-161-1/+1
| | | | | | | | This reverts commit r318397. It broke tools/gold/X86/cache.ll. llvm-svn: 318419
* [FuzzMutate] Fix windows build after rL318407.Igor Laevsky2017-11-161-1/+1
| | | | | | Add correct library dependence. llvm-svn: 318409
* [FuzzMutate] NFC. Move parseModule and writeModule from llvm-isel-fuzzer ↵Igor Laevsky2017-11-161-0/+36
| | | | | | | | into FuzzMutate. This is to be able to reuse them in the llvm-opt-fuzzer. llvm-svn: 318407
* [InstCombine] include 'sub' in the list of narrow-able binopsSanjay Patel2017-11-161-10/+7
| | | | | | | | | | | | | | | | | | | | // trunc (binop X, C) --> binop (trunc X, C') // trunc (binop (ext X), Y) --> binop X, (trunc Y) I'm grouping sub with the other binops because that makes the code simpler and the transforms are valid: https://rise4fun.com/Alive/UeF ...so even though we don't expect a sub with constant Op1 or any of the other opcodes with constant Op0 due to canonicalization rules, we might as well handle those situations if non-canonical code somehow reaches this point (it should just make instcombine more efficient in reaching its end goal). This should solve the problem that later manifests in the vectorizers in PR35295: https://bugs.llvm.org/show_bug.cgi?id=35295 llvm-svn: 318404
* [DebugInfo/PDB] Adding getUndecoratedNameEx and IPDB interfaces for ↵Aaron Smith2017-11-168-0/+151
| | | | | | | | | | | IDiaEnumTables and IDiaTable. Initial changes to support debugging PE/COFF files with LLDB on Windows through DIA SDK. There is another set of changes required on the LLDB side before this does anything. Differential Revision: https://reviews.llvm.org/D39517 llvm-svn: 318403
* [SCEV] simplify loop. NFC.Javed Absar2017-11-161-2/+2
| | | | | | Change loop to range-based llvm-svn: 318401
* Test commit. Add a missing dash to the standard llvm file header; NFC.Aaron Smith2017-11-161-1/+1
| | | | llvm-svn: 318400
* [Support][CachePruning] Fix regression in pruning intervalBen Dunbobbin2017-11-161-1/+1
| | | | | | | | | Fixed broken comparison. borked by: rL284966 (see: https://reviews.llvm.org/D25730). Differential Revision: https://reviews.llvm.org/D40119 llvm-svn: 318397
* [asan] Fix size/alignment issues with non-default shadow scaleWalter Lee2017-11-161-2/+5
| | | | | | | | | | | | | | | Fix a couple places where the minimum alignment/size should be a function of the shadow granularity: - alignment of AllGlobals - the minimum left redzone size on the stack Added a test to verify that the metadata_array is properly aligned for shadow scale of 5, to be enabled when we add build support for testing shadow scale of 5. Differential Revision: https://reviews.llvm.org/D39470 llvm-svn: 318395
* Fix pointer EVT in SelectionDAGBuilder::visitAllocaYaxun Liu2017-11-161-9/+7
| | | | | | | | | | | SelectionDAGBuilder::visitAlloca assumes alloca address space is 0, which is incorrect for triple amdgcn---amdgiz and causes isel failure. This patch fixes that. Differential Revision: https://reviews.llvm.org/D40095 llvm-svn: 318392
* [DAGCombine] Enable more srl -> load combinesSam Parker2017-11-161-5/+16
| | | | | | | | | | | | Change the calculation for the desired ValueType for non-sign extending loads, as in those cases we don't care about the higher bits. This creates a smaller ExtVT and allows for such combinations as: (srl (zextload i16, [addr]), 8) -> (zextload i8, [addr + 1]) Differential Revision: https://reviews.llvm.org/D40034 llvm-svn: 318390
* Assert correct removal of SUnit in LatencyPriorityQueueBenjamin Kramer2017-11-161-0/+1
| | | | | | | | | | | | | | | The LatencyPriorityQueue doesn't currently check whether the SU being removed really exists in the Queue. This method fails quietly when SU is not found and removes the last element from the Queue, leading to unexpected behavior. Unfortunately, this only occurs on our custom target, with the custom scheduler. In our case, when remove() is invoked, it removes the wrong SU at the end of the Queue, which is only discovered later when VerifyScheduledDAG() is invoked and finds that some nodes were not scheduled at all. As this is only reproducible with a lot of proprietary code, I'm hopeful this assert is straightforward enough to not necessitate a test. Patch by Ondrej Glasnak! Differential Revision: https://reviews.llvm.org/D40084 llvm-svn: 318387
* [TTI][X86] update costs of interleaved load\store of i64\doubleMohammed Agabaria2017-11-161-0/+6
| | | | | | | | | | | | This patch contains more accurate cost of interelaved load\store of stride 2 for the types int64\double on AVX2. Reviewers: delena, RKSimon, craig.topper, dorit Reviewed By: dorit Differential Revision: https://reviews.llvm.org/D40008 llvm-svn: 318385
* [MachineRegisterInfo] Avoid having dbg.values affect code generationMikael Holmen2017-11-161-2/+2
| | | | | | | | | | | | | | | | | | | | | | Summary: Use use_nodbg_empty() rather than use_empty() in MachineRegisterInfo::EmitLiveInCopies() when determining if a livein register has any uses or not. Otherwise a single dbg.value can make us generate different code, meaning -g would affect code generation. Found when compiling code for my out-of-tree target. Unfortunately I haven't been able to reproduce the problem on X86 or any of the other in-tree targets that I tried, so no test case. Reviewers: MatzeB Reviewed By: MatzeB Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D39044 llvm-svn: 318382
* [IRCE] Fix SCEVExpander's usage in IRCEMax Kazantsev2017-11-161-0/+14
| | | | | | | | | | | | When expanding exit conditions for pre- and postloops, we may end up expanding a recurrency from the loop to in its loop's preheader. This produces incorrect IR. This patch ensures that IRCE uses SCEVExpander correctly and only expands code which is safe to expand in this particular location. Differentian Revision: https://reviews.llvm.org/D39234 llvm-svn: 318381
* [X86] Update TTI to report that v1iX/v1fX types aren't legal for masked ↵Craig Topper2017-11-161-2/+10
| | | | | | | | gather/scatter/load/store. The type legalizer will try to scalarize these operations if it sees them, but there is no handling for scalarizing them. This leads to a fatal error. With this change they will now be scalarized by the mem intrinsic scalarizing pass before SelectionDAG. llvm-svn: 318380
* [SelectionDAG] Use report_fatal_error instead of llvm_unreachable in some ↵Craig Topper2017-11-161-1/+2
| | | | | | | | | | code that can be reached if targets don't configure things correctly. For example, this is currently reachable by X86 if you use a masked store intrinsic with a v1iX type. Using a fatal error seems like a better user experience if someone were to encounter this on a release build. There are several other similar places that have been converted from unreachable to fatal error previously. llvm-svn: 318379
* [SCEV][NFC] Introduce isSafeToExpandAt function to SCEVExpanderMax Kazantsev2017-11-161-0/+5
| | | | | | | | | | | This function checks that: 1) It is safe to expand a SCEV; 2) It is OK to materialize it at the specified location. For example, attempt to expand a loop's AddRec to the same loop's preheader should fail. Differential Revision: https://reviews.llvm.org/D39236 llvm-svn: 318377
* Fix thinko in last commit.Eric Christopher2017-11-161-1/+1
| | | | llvm-svn: 318374
* Add NDEBUG checks around LLVM_DUMP_METHOD functions for Wunused-function ↵Eric Christopher2017-11-162-2/+8
| | | | | | warnings. llvm-svn: 318373
* Fix APInt bit size in processDbgDeclaresYaxun Liu2017-11-161-1/+1
| | | | | | | | | | | | | processDbgDeclares assumes pointer size is the same for different addr spaces. It uses pointer size for addr space 0 for all pointers, which causes assertion in stripAndAccumulateInBoundsConstantOffsets for amdgcn---amdgiz since pointer in addr space 5 has different size than in addr space 0. This patch fixes that. Differential Revision: https://reviews.llvm.org/D40085 llvm-svn: 318370
* [asan] Fallback to non-ifunc dynamic shadow on android<22.Evgeniy Stepanov2017-11-161-1/+3
| | | | | | | | | | | | Summary: Android < 22 does not support ifunc. Reviewers: pcc Subscribers: srhines, kubamracek, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D40116 llvm-svn: 318369
* [X86] Custom type legalize v2f32 masked gathers instead of trying to cleanup ↵Craig Topper2017-11-161-26/+28
| | | | | | after type legalization. llvm-svn: 318368
* LTO: clarify why we need to gracefully handle sys::fs::rename failuresBob Haarman2017-11-161-7/+9
| | | | | | | | | | | | Reviewers: pcc, rafael Reviewed By: pcc Subscribers: mehdi_amini, llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D40094 llvm-svn: 318362
* bpf: enable llvm-objdump to print out symbolized jmp targetYonghong Song2017-11-161-0/+34
| | | | | | | | | | | | | | | | | | Add hook in BPF backend so that llvm-objdump can print out the jmp target with label names, e.g., ... if r1 != 2 goto 6 <LBB0_2> ... goto 7 <LBB0_4> ... LBB0_2: ... LBB0_4: ... Signed-off-by: Yonghong Song <yhs@fb.com> Acked-by: Alexei Starovoitov <ast@kernel.org> llvm-svn: 318358
* [globalisel][tablegen] Generate rule coverage and use it to identify ↵Daniel Sanders2017-11-168-28/+173
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | untested rules Summary: This patch adds a LLVM_ENABLE_GISEL_COV which, like LLVM_ENABLE_DAGISEL_COV, causes TableGen to instrument the generated table to collect rule coverage information. However, LLVM_ENABLE_GISEL_COV goes a bit further than LLVM_ENABLE_DAGISEL_COV. The information is written to files (${CMAKE_BINARY_DIR}/gisel-coverage-* by default). These files can then be concatenated into ${LLVM_GISEL_COV_PREFIX}-all after which TableGen will read this information and use it to emit warnings about untested rules. This technique could also be used by SelectionDAG and can be further extended to detect hot rules and give them priority over colder rules. Usage: * Enable LLVM_ENABLE_GISEL_COV in CMake * Build the compiler and run some tests * cat gisel-coverage-[0-9]* > gisel-coverage-all * Delete lib/Target/*/*GenGlobalISel.inc* * Build the compiler Known issues: * ${LLVM_GISEL_COV_PREFIX}-all must be generated as a manual step due to a lack of a portable 'cat' command. It should be the concatenation of all ${LLVM_GISEL_COV_PREFIX}-[0-9]* files. * There's no mechanism to discard coverage information when the ruleset changes Depends on D39742 Reviewers: ab, qcolombet, t.p.northover, aditya_nandakumar, rovka Reviewed By: rovka Subscribers: vsk, arsenm, nhaehnle, mgorny, kristof.beyls, javed.absar, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D39747 llvm-svn: 318356
* Try to fix WebAssembly build after r318352Reid Kleckner2017-11-161-2/+2
| | | | llvm-svn: 318355
* [GVNHoist] Fix a signed/unsigned comparison warning that occurs in 32-bit ↵Craig Topper2017-11-161-1/+1
| | | | | | | | builds with gcc. std::distance returns ptrdiff_t which is signed. 64-bit builds don't notice because type promotion widens the unsigned first. llvm-svn: 318354
* [CodeGen] Fix the branch probability assertion in r318202Rong Xu2017-11-161-2/+4
| | | | | | | Due to integer precision, we might have numerator greater than denominator in the branch probability scaling. Add a check to prevent this from happening. llvm-svn: 318353
* Add backend name to Target to enable runtime info to be fed back into TableGenDaniel Sanders2017-11-1515-38/+42
| | | | | | | | | | | | | | | | | | | | | | Summary: Make it possible to feed runtime information back to tablegen to enable profile-guided tablegen-eration, detection of untested tablegen definitions, etc. Being a cross-compiler by nature, LLVM will potentially collect data for multiple architectures (e.g. when running 'ninja check'). We therefore need a way for TableGen to figure out what data applies to the backend it is generating at the time. This patch achieves that by including the name of the 'def X : Target ...' for the backend in the TargetRegistry. Reviewers: qcolombet Reviewed By: qcolombet Subscribers: jholewinski, arsenm, jyknight, aditya_nandakumar, sdardis, nemanjai, ab, nhaehnle, t.p.northover, javed.absar, qcolombet, llvm-commits, fedor.sergeev Differential Revision: https://reviews.llvm.org/D39742 llvm-svn: 318352
* [AArch64] Adjust the cost model for Exynos M1 and M2Evandro Menezes2017-11-151-4/+14
| | | | | | Fix the modeling of FP stores. llvm-svn: 318351
* [GISel][NFC]: Move getOpcodeDef from the LegalizationArtifactCombiner into ↵Aditya Nandakumar2017-11-151-0/+16
| | | | | | GlobalISel/Utils for use elsewhere llvm-svn: 318350
* AMDGPU: Replace i64 add/sub loweringMatt Arsenault2017-11-155-9/+146
| | | | | | | | | | | | | | | Use VOP3 add/addc like usual. This has some tradeoffs. Inline immediates fold a little better, but other constants are worse off. SIShrinkInstructions could be made smarter to handle these cases. This allows us to avoid selecting scalar adds where we need to track the carry in scc and replace its users. This makes it easier to use the carryless VALU adds. llvm-svn: 318340
* [AArch64] Refactor the loads and stores optimizerEvandro Menezes2017-11-151-143/+143
| | | | | | | | | Move remaining inline matching of instructions of some optimizations into separate functions, like in the other optimizations. Otherwise, NFC. Differential revision: https://reviews.llvm.org/D40090 llvm-svn: 318335
* [X86] Add some explanatory comments to the ProcessorFeatures enum in Host.cpp.Craig Topper2017-11-151-1/+4
| | | | llvm-svn: 318331
* [X86] Add a return to the end of a switch to prevent an accidental ↵Craig Topper2017-11-151-0/+1
| | | | | | fallthrough in the future. llvm-svn: 318330
* [InstCombine] trunc (binop X, C) --> binop (trunc X, C')Sanjay Patel2017-11-151-4/+17
| | | | | | | | | Note that one-use and shouldChangeType() are checked ahead of the switch. Without the narrowing folds, we can produce inferior vector code as shown in PR35299: https://bugs.llvm.org/show_bug.cgi?id=35299 llvm-svn: 318323
* Use TempFile in lto caching.Rafael Espindola2017-11-152-30/+46
| | | | | | | | | | This requires a small change to TempFile: allowing a discard after a failed keep. With this the cache now handles signals and reuses a fd instead of reopening the file. llvm-svn: 318322
* [PowerPC] Implement mayBeEmittedAsTailCall for PPCSean Fertile2017-11-152-0/+39
| | | | | | | | | Implements TargetLowering callback 'mayBeEmittedAsTailCall' that enables CodeGenPrepare to duplicate returns when they might enable a tail-call. Differential Revision: https://reviews.llvm.org/D39777 llvm-svn: 318321
* [InstCombine] Salvage debug info during initial DCEReid Kleckner2017-11-151-0/+1
| | | | | | | | | | | InstCombine salvages debug info for every instruction it erases from its worklist, but it wasn't doing it during its initial DCE when populating its worklist. This fixes that. This should help improve availability of 'this' in optimized debug info when casts are necessary. llvm-svn: 318320
* [AArch64] Adjust the cost model for Exynos M1 and M2Evandro Menezes2017-11-151-17/+14
| | | | | | | Fix the modeling of loads and stores using the pre or post indexed addressing modes. llvm-svn: 318312
* [X86] Add CBW/CDQ/CDQE/CQO/CWD/CWDE to WriteALU schedule classSimon Pilgrim2017-11-152-32/+31
| | | | | | | | Some CPUs are already overriding these sign extension instructions but we should be able to use the WriteALU schedule class by default. Differential Revision: https://reviews.llvm.org/D39899 llvm-svn: 318308
* [SLP] Added more missed optimization remarksAdam Nemet2017-11-151-14/+74
| | | | | | | | | | | | | | | | | | | | Summary: Added more remarks to SLP pass, in particular "missed" optimization remarks. Also proposed several tests for new functionality. Patch by Vladimir Miloserdov! For reference you may look at: https://reviews.llvm.org/rL302811 Reviewers: anemet, fhahn Reviewed By: anemet Subscribers: javed.absar, lattner, petecoup, yakush, llvm-commits Differential Revision: https://reviews.llvm.org/D38367 llvm-svn: 318307
* [PowerPC] Split out the tailcall calling convention checks. NFC.Sean Fertile2017-11-151-11/+19
| | | | | | | | Move the calling convention checks for tail-call eligibility for the 64-bit SysV ABI into a separate function. This is so that it can be shared with 'mayBeEmittedAsTailCall' in a subsequent change. llvm-svn: 318305
* [(new) Pass Manager] instantiate SimplifyCFG with the same options as the old PMSanjay Patel2017-11-151-2/+7
| | | | | | | | | | | | | | | | | | This is a recommit of r316869 which was speculatively reverted with r317444 and subsequently shown to not be the cause of PR35210. That crash should be fixed after r318237. Original commit message: The old PM sets the options of what used to be known as "latesimplifycfg" on the instantiation after the vectorizers have run, so that's what we'redoing here. FWIW, there's a later SimplifyCFGPass instantiation in both PMs where we do not set the "late" options. I'm not sure if that's intentional or not. Differential Revision: https://reviews.llvm.org/D39407 llvm-svn: 318299
* [Reassociate] simplify code; NFCISanjay Patel2017-11-151-6/+3
| | | | llvm-svn: 318298
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