diff options
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 17 |
1 files changed, 16 insertions, 1 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 3c3657e1f56..cab17fb2d75 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -12223,9 +12223,24 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N, cast<StoreSDNode>(N)->getMemOperand()); } + // STORE Constant:i32<0> -> STORE<trunc to i32> Constant:i64<0> + // So it can increase the chance of CSE constant construction. + EVT VT = N->getOperand(1).getValueType(); + if (Subtarget.isPPC64() && !DCI.isBeforeLegalize() && + isa<ConstantSDNode>(N->getOperand(1)) && VT == MVT::i32) { + SDValue Const64 = DAG.getConstant(N->getConstantOperandVal(1), dl, + MVT::i64); + // DAG.getTruncStore() can't be used here because it doesn't accept + // the general (base + offset) addressing mode. + // So we use UpdateNodeOperands and setTruncatingStore instead. + DAG.UpdateNodeOperands(N, N->getOperand(0), Const64, N->getOperand(2), + N->getOperand(3)); + cast<StoreSDNode>(N)->setTruncatingStore(true); + return SDValue(N, 0); + } + // For little endian, VSX stores require generating xxswapd/lxvd2x. // Not needed on ISA 3.0 based CPUs since we have a non-permuting store. - EVT VT = N->getOperand(1).getValueType(); if (VT.isSimple()) { MVT StoreVT = VT.getSimpleVT(); if (Subtarget.needsSwapsForVSXMemOps() && |
