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* [SubtargetFeatures] Add operator< for comparing SubtargetInfoKV objects. NFCICraig Topper2019-03-041-4/+1
| | | | | | Use instead of passing a lambda to std::is_sorted. This is more consistent with SubtargetFeatureKV. llvm-svn: 355300
* [SubtargetFeatures] Don't call ApplyFeatureFlag if the feature name is '+help'Craig Topper2019-03-041-2/+2
| | | | | | Just print the help and stop. Otherwise we'll print a message about it not being a real feature name after printing the help text. llvm-svn: 355299
* [SubtargetFeatuers] Simplify the code used to imply features from CPU name.Craig Topper2019-03-041-14/+7
| | | | | | If we make SetImpliedBits OR features outside of its loop, we can reuse it for the first round of implying features for CPUs. llvm-svn: 355298
* [WebAssembly] Delete ThrowUnwindDest map from WasmEHFuncInfoHeejin Ahn2019-03-034-26/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Before when we implemented the first EH proposal, 'catch <tag>' instruction may not catch an exception so there were multiple EH pads an exception can unwind to. That means a BB could have multiple EH pad successors. Now after we switched to the new proposal, every 'catch' instruction catches an exception, and there is only one catchpad per catchswitch, so we at most have one EH pad successor, making `ThrowUnwindDest` map in `WasmEHInfo` unnecessary. Keeping `ThrowUnwindDest` map in `WasmEHInfo` has its own problems, because other optimization passes can split a BB that contains possibly throwing calls (previously invokes), and we have to update the map every time that happens, which is not easy for common CodeGen passes. This also correctly updates successor info in LateEHPrepare when we add a rethrow instruction. Reviewers: dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D58486 llvm-svn: 355296
* [ValueTracking] do not try to peek through bitcasts in ↵Sanjay Patel2019-03-031-3/+1
| | | | | | | | | | computeKnownBitsFromAssume() There are no tests for this case, and I'm not sure how it could ever work, so I'm just removing this option from the matcher. This should fix PR40940: https://bugs.llvm.org/show_bug.cgi?id=40940 llvm-svn: 355292
* [DemandedBits] Remove some redundancy in the work listFangrui Song2019-03-031-8/+9
| | | | | | | | | InputIsKnownDead check is shared by all operands. Compute it once. For non-integer instructions, use Visited.insert(I).second to replace a find() and an insert(). llvm-svn: 355290
* Remove unused variable. NFCI.Simon Pilgrim2019-03-031-1/+0
| | | | llvm-svn: 355289
* [X86] getShuffleScalarElt - peek through insert/extract subvector nodes.Simon Pilgrim2019-03-031-0/+23
| | | | llvm-svn: 355288
* [X86] Pull out combineToConsecutiveLoads helper. NFCI.Simon Pilgrim2019-03-031-17/+23
| | | | llvm-svn: 355287
* Remove large amount of empty lines mid-file. NFCKristina Brooks2019-03-031-9/+0
| | | | llvm-svn: 355286
* [DemandedBits] Optimize a find()+insert pattern with try_emplace and ↵Fangrui Song2019-03-031-8/+3
| | | | | | APInt::operator|= llvm-svn: 355284
* [llvm] [Support] Reimplement getMainExecutable() using sysctl on NetBSDMichal Gorny2019-03-031-2/+18
| | | | | | | | | | | | | | | | Use sysctl() to implement getMainExecutable() on NetBSD, rather than trying to guess the correct path from argv[0]. This is one of the fixes to recent clang-check-mac-libcxx-fixed-compilation-db.cpp test failure on NetBSD. This has been historically done on both FreeBSD and NetBSD in r303015, and reverted in r303285 due to buggy implementation on FreeBSD. However, FWIK the NetBSD implementation does not suffer from the same bugs and is more reliable than playing with argv[0]. Differential Revision: https://reviews.llvm.org/D56975 llvm-svn: 355283
* [X86] Prefer VPBLENDD for v2i64/v4i64 blends with AVX2.Craig Topper2019-03-031-3/+37
| | | | | | | | We were using VPBLENDW for v2i64 and VBLENDPD for v4i64. VPBLENDD has better throughput than VPBLENDW on some CPUs so it makes sense to use it when possible. VBLENDPD will probably become VBLENDD during execution domain fixing, but we might as well use integer in isel while we can. This should work around some issues with the domain fixing pass prefering PBLENDW when we start with PBLENDW. There may still be some v8i16 cases that could use PBLENDD. llvm-svn: 355281
* [InstCombine] move add after smin/smaxSanjay Patel2019-03-021-3/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Follow-up to rL355221. This isn't specifically called for within PR14613, but we'll get there eventually if it's not already requested in some other bug report. https://rise4fun.com/Alive/5b0 Name: smax Pre: WillNotOverflowSignedSub(C1,C0) %a = add nsw i8 %x, C0 %cond = icmp sgt i8 %a, C1 %r = select i1 %cond, i8 %a, i8 C1 => %c2 = icmp sgt i8 %x, C1-C0 %u2 = select i1 %c2, i8 %x, i8 C1-C0 %r = add nsw i8 %u2, C0 Name: smin Pre: WillNotOverflowSignedSub(C1,C0) %a = add nsw i32 %x, C0 %cond = icmp slt i32 %a, C1 %r = select i1 %cond, i32 %a, i32 C1 => %c2 = icmp slt i32 %x, C1-C0 %u2 = select i1 %c2, i32 %x, i32 C1-C0 %r = add nsw i32 %u2, C0 llvm-svn: 355272
* Use SDValue::getConstantOperandAPInt helper where possible. NFCI.Simon Pilgrim2019-03-022-7/+4
| | | | llvm-svn: 355267
* [llvm-objdump] Should print unknown d_tag in hex formatXing GUO2019-03-021-3/+3
| | | | | | | | | | | | | | | | | | Summary: Currently, `llvm-objdump` prints "unknown" instead of d_tag value in hex format. Because getDynamicTagAsString returns "unknown" rather than empty string. Reviewers: grimar, jhenderson Reviewed By: jhenderson Subscribers: rupprecht, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D58763 llvm-svn: 355262
* [WebAssembly] Expand operations not supported by SIMDThomas Lively2019-03-021-0/+17
| | | | | | | | | | | | | | | | | | Summary: This prevents crashes in instruction selection when these operations are used. The tests check that the scalar version of the instruction is used where applicable, although some expansions do not use the scalar version. Reviewers: aheejin Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, sunfish, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D58859 llvm-svn: 355261
* [X86] Improve use of SHLD/SHRDAmaury Sechet2019-03-021-0/+6
| | | | | | | | | | | | | | | Summary: This extends the variety of pattern that can generate a SHLD instead of using two shifts. This fixes a regression that would be introduced by D57367 or D33587 Reviewers: RKSimon, craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D57389 llvm-svn: 355260
* [SCEV] Handle case where MaxBECount is less precise than ExactBECount for OR.Florian Hahn2019-03-021-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | In some cases, MaxBECount can be less precise than ExactBECount for AND and OR (the AND case was PR26207). In the OR test case, both ExactBECounts are undef, but MaxBECount are different, so we hit the assertion below. This patch uses the same solution the AND case already uses. Assertion failed: ((isa<SCEVCouldNotCompute>(ExactNotTaken) || !isa<SCEVCouldNotCompute>(MaxNotTaken)) && "Exact is not allowed to be less precise than Max"), function ExitLimit This patch also consolidates test cases for both AND and OR in a single test case. Fixes https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=13245 Reviewers: sanjoy, efriedma, mkazantsev Reviewed By: sanjoy Differential Revision: https://reviews.llvm.org/D58853 llvm-svn: 355259
* [SCEV] Remove undef check for SCEVConstant (NFC)Florian Hahn2019-03-021-2/+0
| | | | | | | | | | | | | The value stored in SCEVConstant is of type ConstantInt*, which can never be UndefValue. So we should never hit that code. Reviewers: mkazantsev, sanjoy Reviewed By: sanjoy Differential Revision: https://reviews.llvm.org/D58851 llvm-svn: 355257
* Revert "[DWARFFormValue] Cleanup DWARFFormValue interface. (2/2) (NFC)"Vlad Tsyrklevich2019-03-024-22/+21
| | | | | | This reverts commit r355233, it was causing UBSan failures. llvm-svn: 355255
* Revert "[WebAssembly][WIP] Expand operations not supported by SIMD"Thomas Lively2019-03-021-17/+0
| | | | | | This was accidentally committed without tests or review. llvm-svn: 355254
* [ProfileData] Sort FuncData before iteration to remove non-determinismMandeep Singh Grang2019-03-021-6/+22
| | | | | | | | | | | | | | Reviewers: rsmith, bogner, dblaikie Reviewed By: dblaikie Subscribers: Hahnfeld, jdoerfert, vsk, dblaikie, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D57986 llvm-svn: 355252
* [WebAssembly][WIP] Expand operations not supported by SIMDThomas Lively2019-03-021-0/+17
| | | | llvm-svn: 355247
* [tblgen] Track CodeInit origins when possibleDaniel Sanders2019-03-022-8/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Add an SMLoc to CodeInit that records the source line it originated from. This allows tablegen to point precisely at portions of code when reporting errors within the CodeInit. For example, in the upcoming GlobalISel combiner, it can report undefined expansions and point at the instance of the expansion. This is achieved using something like: SMLoc::getFromPointer(SMLoc::getPointer() + (StringRef - CodeInit::getValue())) The location is lost when producing a CodeInit by string concatenation so a fallback SMLoc is required (e.g. the Record::getLoc()) but that's pretty rare for CodeInits. There's a reasonable case for extending tracking of a couple other Init objects, for example StringInit's are often parsed and it would be good to point inside the string when reporting errors about that. However, location tracking also harms de-duplication. This is fine for CodeInit where there's only a few hundred of them (~160 for X86) and it may be worth it for StringInit (~86k up to ~1.9M for roughly 15MB increase for X86). However the origin tracking would be a _terrible_ idea for IntInit, BitInit, and UnsetInit. I haven't measured either of those three but BitInit would most likely be on the order of increasing the current 2 BitInit values up to billions. Reviewers: volkan, aditya_nandakumar, bogner, paquette, aemerson Reviewed By: paquette Subscribers: javed.absar, kristof.beyls, dexonsmith, llvm-commits, kristina Tags: #llvm Differential Revision: https://reviews.llvm.org/D58141 llvm-svn: 355245
* Try to fix Windows bots after r355226.Paul Robinson2019-03-011-1/+2
| | | | | | Windows has two path separator characters. llvm-svn: 355235
* [DWARFFormValue] Cleanup DWARFFormValue interface. (2/2) (NFC)Jonas Devlieghere2019-03-014-21/+22
| | | | | | | Continues the work started in r354941. Changes (all but one) uses of the extractValue to static createFromData. llvm-svn: 355233
* [DWARF] Make -g with empty assembler source work better.Paul Robinson2019-03-013-12/+47
| | | | | | | | | | | | | This was sometimes causing clang or llvm-mc to crash, and in other cases could emit a bogus DWARF line-table header. I did an interim patch in r352541; this patch should be a cleaner and more complete fix, and retains the test. Addresses PR40538. Differential Revision: https://reviews.llvm.org/D58750 llvm-svn: 355226
* [TableGen][SelectionDAG][X86] Add specific isel matchers for ↵Craig Topper2019-03-015-59/+59
| | | | | | | | | | | | | | immAllZerosV/immAllOnesV. Remove bitcasts from X86 patterns that are no longer necessary. Previously we had build_vector PatFrags that called ISD::isBuildVectorAllZeros/Ones. Internally the ISD::isBuildVectorAllZeros/Ones look through bitcasts, but we aren't able to take advantage of that in isel. Instead of we have to canonicalize the types of the all zeros/ones build_vectors and insert bitcasts. Then we have to pattern match those exact bitcasts. By emitting specific matchers for these 2 nodes, we can make isel look through any bitcasts without needing to explicitly match them. We should also be able to remove the canonicalization to vXi32 from lowering, but I've left that for a follow up. This removes something like 40,000 bytes from the X86 isel table. Differential Revision: https://reviews.llvm.org/D58595 llvm-svn: 355224
* [ValueTracking] Known bits support for unsigned saturating add/subNikita Popov2019-03-011-0/+31
| | | | | | | | | | | | | | | | We have two sources of known bits: 1. For adds leading ones of either operand are preserved. For sub leading zeros of LHS and leading ones of RHS become leading zeros in the result. 2. The saturating math is a select between add/sub and an all-ones/ zero value. As such we can carry out the add/sub known bits calculation, and only preseve the known one/zero bits respectively. Differential Revision: https://reviews.llvm.org/D58329 llvm-svn: 355223
* [InstCombine] Extend saturating idempotent atomicrmw transform to FPPhilip Reames2019-03-011-2/+10
| | | | | | | | I'm assuming that the nan propogation logic for InstructonSimplify's handling of fadd and fsub is correct, and applying the same to atomicrmw. Differential Revision: https://reviews.llvm.org/D58836 llvm-svn: 355222
* [InstCombine] move add after umin/umaxSanjay Patel2019-03-011-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the motivating cases from PR14613: https://bugs.llvm.org/show_bug.cgi?id=14613 ...moving the add enables us to narrow the min/max which eliminates zext/trunc which enables signficantly better vectorization. But that bug is still not completely fixed. https://rise4fun.com/Alive/5KQ Name: umax Pre: C1 u>= C0 %a = add nuw i8 %x, C0 %cond = icmp ugt i8 %a, C1 %r = select i1 %cond, i8 %a, i8 C1 => %c2 = icmp ugt i8 %x, C1-C0 %u2 = select i1 %c2, i8 %x, i8 C1-C0 %r = add nuw i8 %u2, C0 Name: umin Pre: C1 u>= C0 %a = add nuw i32 %x, C0 %cond = icmp ult i32 %a, C1 %r = select i1 %cond, i32 %a, i32 C1 => %c2 = icmp ult i32 %x, C1-C0 %u2 = select i1 %c2, i32 %x, i32 C1-C0 %r = add nuw i32 %u2, C0 llvm-svn: 355221
* Revert "[MIPS GlobalISel] Fix mul operands"Vlad Tsyrklevich2019-03-011-4/+0
| | | | | | | This reverts commit r355178, it is causing ASan failures on the sanitizer bots. llvm-svn: 355219
* [LICM] Infer proper alignment from loads during scalar promotionPhilip Reames2019-03-011-3/+23
| | | | | | | | | | This patch fixes an issue where we would compute an unnecessarily small alignment during scalar promotion when no store is not to be guaranteed to execute, but we've proven load speculation safety. Since speculating a load requires proving the existing alignment is valid at the new location (see Loads.cpp), we can use the alignment fact from the load. For non-atomics, this is a performance problem. For atomics, this is a correctness issue, though an *incredibly* rare one to see in practice. For atomics, we might not be able to lower an improperly aligned load or store (i.e. i32 align 1). If such an instruction makes it all the way to codegen, we *may* fail to codegen the operation, or we may simply generate a slow call to a library function. The part that makes this super hard to see in practice is that the memory location actually *is* well aligned, and instcombine knows that. So, to see a failure, you have to have a) hit the bug in LICM, b) somehow hit a depth limit in InstCombine/ValueTracking to avoid fixing the alignment, and c) then have generated an instruction which fails codegen rather than simply emitting a slow libcall. All around, pretty hard to hit. Differential Revision: https://reviews.llvm.org/D58809 llvm-svn: 355217
* [InstCombine] Extend "idempotent" atomicrmw optimizations to floating pointPhilip Reames2019-03-011-2/+17
| | | | | | | | | | An idempotent atomicrmw is one that does not change memory in the process of execution. We have already added handling for the various integer operations; this patch extends the same handling to floating point operations which were recently added to IR. Note: At the moment, we canonicalize idempotent fsub to fadd when ordering requirements prevent us from using a load. As discussed in the review, I will be replacing this with canonicalizing both floating point ops to integer ops in the near future. Differential Revision: https://reviews.llvm.org/D58251 llvm-svn: 355210
* Revert "[WebAssembly] Lower SIMD shifts since they are fixed in V8"Thomas Lively2019-03-011-0/+5
| | | | | | They weren't fixed in V8. Oops. llvm-svn: 355208
* Hide two unused debugging methods, NFCI.Jonas Hahnfeld2019-03-012-0/+8
| | | | | | | | GCC correctly moans that PlainCFGBuilder::isExternalDef(llvm::Value*) and StackSafetyDataFlowAnalysis::verifyFixedPoint() are defined but not used in Release builds. Hide them behind 'ifndef NDEBUG'. llvm-svn: 355205
* Try to fix NetBSD buildbot breakage introduced in D57463.Manman Ren2019-03-011-0/+1
| | | | | | By including the header file in the source. llvm-svn: 355202
* [ARM] Fix FP16 stack loads/stores for Thumb2 with frame pointerOliver Stannard2019-03-011-2/+2
| | | | | | | | | | The new addressing mode added for the v8.2A FP16 instructions uses bit 8 of the immediate to encode the sign of the offset, like the other FP loads/stores, so need to be treated the same way. Differential revision: https://reviews.llvm.org/D58816 llvm-svn: 355201
* [ARM] Consider undefined-on-NaN conditions in checkVSELConstraintsOliver Stannard2019-03-011-5/+6
| | | | | | | | | | This function was not checking for the condition code variants which are undefined if either input is NaN, so we were missing selection of the VSEL instruction in some cases when using -fno-honor-nans or -ffast-math. Differential revision: https://reviews.llvm.org/D58812 llvm-svn: 355199
* [yaml2obj] - Allow setting custom sh_info for RawContentSection sections.George Rimar2019-03-011-0/+1
| | | | | | | | | | | This is for tweaking SHT_SYMTAB sections. Their sh_info contains the (number of symbols + 1) usually. But for creating invalid inputs for test cases it would be convenient to allow explicitly override this field from YAML. Differential revision: https://reviews.llvm.org/D58779 llvm-svn: 355193
* [ARM GlobalISel] Support G_CTLZ for Thumb2Diana Picus2019-03-011-7/+0
| | | | | | Same as ARM mode but with different opcode. llvm-svn: 355191
* [Tablegen] Add support for the !mul operator.Nicola Zaghen2019-03-014-5/+15
| | | | | | | | | This is a small addition to arithmetic operations that improves expressiveness of the language. Differential Revision: https://reviews.llvm.org/D58775 llvm-svn: 355187
* [CommandLine] Allow grouping options which can have values.Igor Kudrin2019-03-011-21/+24
| | | | | | | | | | | | | | | | This patch allows all forms of values for options to be used at the end of a group. With the fix, it is possible to follow the way GNU binutils tools handle grouping options better. For example, the -j option can be used with objdump in any of the following ways: $ objdump -d -j .text a.o $ objdump -d -j.text a.o $ objdump -dj .text a.o $ objdump -dj.text a.o Differential Revision: https://reviews.llvm.org/D58711 llvm-svn: 355185
* [CommandLine] Do not crash if an option has both ValueRequired and Grouping.Igor Kudrin2019-03-011-4/+7
| | | | | | | | | | | | If an option, which requires a value, has a `cl::Grouping` formatting modifier, it works well as far as it is used at the end of a group, or as a separate argument. However, if the option appears accidentally in the middle of a group, the program just crashes. This patch prints an error message instead. Differential Revision: https://reviews.llvm.org/D58499 llvm-svn: 355184
* [AMDGPU] Mark ds instructions as meybeAtomicStanislav Mekhanoshin2019-03-011-0/+1
| | | | | | | | | | | | These were not recognized as potential atomics by memory legalizer. The test was working not because legalizer did a right thing, but because it has skipped all these instructions. When I have fixed DS desciption test started to fail because region address has changed from 4 to 2 a while ago. Differential Revision: https://reviews.llvm.org/D58802 llvm-svn: 355179
* [MIPS GlobalISel] Fix mul operandsPetar Avramovic2019-03-011-0/+4
| | | | | | | | | | | | | | | | | Unsigned mul high for MIPS32 is selected into two PseudoInstructions: PseudoMULTu and PseudoMFHI that use accumulator register class ACC64 for some of its operands. Registers in this class have appropriate hi and lo register as subregisters: $lo0 and $hi0 are subregisters of $ac0 etc. mul instruction implicit-defs $lo0 and $hi0 according to MipsInstrInfo.td. In functions where mul and PseudoMULTu are present fastRegisterAllocator will "run out of registers during register allocation" because 'calcSpillCost' for $ac0 will return spillImpossible because subregisters $lo0 and $hi0 of $ac0 are reserved by mul instruction above. A solution is to mark implicit-defs of $lo0 and $hi0 as dead in mul instruction. Differential Revision: https://reviews.llvm.org/D58715 llvm-svn: 355178
* [MIPS GlobalISel] Select G_UMULHPetar Avramovic2019-03-013-1/+25
| | | | | | | | Legalize G_UMULO and select G_UMULH for MIPS32. Differential Revision: https://reviews.llvm.org/D58714 llvm-svn: 355177
* [ConstantHoisting] Call cleanup() in ConstantHoistingPass::runImpl to avoid ↵Fangrui Song2019-03-011-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | dangling elements in ConstIntInfoVec for new PM Summary: ConstIntInfoVec contains elements extracted from the previous function. In new PM, releaseMemory() is not called and the dangling elements can cause segfault in findConstantInsertionPoint. Rename releaseMemory() to cleanup() to deliver the idea that it is mandatory and call cleanup() in ConstantHoistingPass::runImpl to fix this. Reviewers: ormris, zzheng, dmgreen, wmi Reviewed By: ormris, wmi Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D58589 llvm-svn: 355174
* [Subtarget] Remove static global constructor call from the tablegened ↵Craig Topper2019-03-011-18/+14
| | | | | | | | | | | | | | | | | | subtarget feature tables Subtarget features are stored in a std::bitset that has been subclassed. There is a special constructor to allow the tablegen files to provide a list of bits to initialize the std::bitset to. This constructor isn't constexpr and std::bitset doesn't support many constexpr operations either. This results in a static global constructor being used to initialize the feature bitsets in these files at startup. To fix this I've introduced a new FeatureBitArray class that holds three 64-bit values representing the initial bit values and taught tablegen to emit hex constants for them based on the feature enum values. This makes the tablegen files less readable than they were before. I can add the list of features back as a comment if we think that's important. I've added a method to convert from this class into the std::bitset subclass we had before. I considered making the new FeatureBitArray class just implement the std::bitset interface we need instead, but thought I'd see how others felts about that first. I've simplified the interfaces to SetImpliedBits and ClearImpliedBits a little minimize the number of times we need to convert to the bitset. This removes about 27K from my local release+asserts build of llc. Differential Revision: https://reviews.llvm.org/D58520 llvm-svn: 355167
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