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| author | Amaury Sechet <deadalnix@gmail.com> | 2019-03-02 02:44:16 +0000 |
|---|---|---|
| committer | Amaury Sechet <deadalnix@gmail.com> | 2019-03-02 02:44:16 +0000 |
| commit | f24abf651199f8abc65671a4928cc9f2df6ab2d1 (patch) | |
| tree | 85f7f7d629ca64d2ea19ae60fe68185150ccf67c /llvm/lib | |
| parent | 98f11a7d75b54b44b3b136b537644fd3f6d77239 (diff) | |
| download | bcm5719-llvm-f24abf651199f8abc65671a4928cc9f2df6ab2d1.tar.gz bcm5719-llvm-f24abf651199f8abc65671a4928cc9f2df6ab2d1.zip | |
[X86] Improve use of SHLD/SHRD
Summary:
This extends the variety of pattern that can generate a SHLD instead of using two shifts.
This fixes a regression that would be introduced by D57367 or D33587
Reviewers: RKSimon, craig.topper
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D57389
llvm-svn: 355260
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index de666798b03..fe2fd090e21 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -37425,6 +37425,12 @@ static SDValue combineOr(SDNode *N, SelectionDAG &DAG, SDValue Sum = ShAmt1.getOperand(0); if (auto *SumC = dyn_cast<ConstantSDNode>(Sum)) { SDValue ShAmt1Op1 = ShAmt1.getOperand(1); + if (ShAmt1Op1.getOpcode() == ISD::AND && + isa<ConstantSDNode>(ShAmt1Op1.getOperand(1)) && + ShAmt1Op1.getConstantOperandVal(1) == (Bits - 1)) { + ShMsk1 = ShAmt1Op1; + ShAmt1Op1 = ShAmt1Op1.getOperand(0); + } if (ShAmt1Op1.getOpcode() == ISD::TRUNCATE) ShAmt1Op1 = ShAmt1Op1.getOperand(0); if ((SumC->getAPIntValue() == Bits || |
