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* Add support to match @llvm.prefetch to pld / pldw / pli. rdar://8601536.Evan Cheng2010-11-035-47/+47
| | | | llvm-svn: 118152
* Put the PC encoding in the correct bit position.Bill Wendling2010-11-031-1/+1
| | | | llvm-svn: 118151
* Invert these branches by default, it makes assembly comparisons a littleEric Christopher2010-11-031-2/+2
| | | | | | easier to read. llvm-svn: 118148
* The MC code couldn't handle ARM LDR instructions with negative offsets:Bill Wendling2010-11-036-52/+140
| | | | | | | | | | | | vldr.64 d1, [r0, #-32] The problem was with how the addressing mode 5 encodes the offsets. This change makes sure that the way offsets are handled in addressing mode 5 is consistent throughout the MC code. It involves re-refactoring the "getAddrModeImmOpValue" method into an "Imm12" and "addressing mode 5" version. But not to worry! The majority of the duplicated code has been unified. llvm-svn: 118144
* Fix DAGCombiner to avoid going into an infinite loop when itDan Gohman2010-11-031-1/+36
| | | | | | | encounters (and:i64 (shl:i64 (load:i64), 1), 0xffffffff). This fixes rdar://8606584. llvm-svn: 118143
* Remove unused function.Jim Grosbach2010-11-032-9/+0
| | | | llvm-svn: 118141
* Remove the no longer used 'Modifier' optional operand to the ARMJim Grosbach2010-11-032-17/+8
| | | | | | printOperand() asm printer helper functions. rdar://8425198 llvm-svn: 118140
* Remove unused function.Jim Grosbach2010-11-032-12/+0
| | | | llvm-svn: 118139
* Break ARM addrmode4 (load/store multiple base address) into its constituentJim Grosbach2010-11-039-104/+90
| | | | | | | parts. Represent the operation mode as an optional operand instead. rdar://8614429 llvm-svn: 118137
* Two sets of changes. Sorry they are intermingled.Evan Cheng2010-11-039-110/+155
| | | | | | | | | | | | | 1. Fix pre-ra scheduler so it doesn't try to push instructions above calls to "optimize for latency". Call instructions don't have the right latency and this is more likely to use introduce spills. 2. Fix if-converter cost function. For ARM, it should use instruction latencies, not # of micro-ops since multi-latency instructions is completely executed even when the predicate is false. Also, some instruction will be "slower" when they are predicated due to the register def becoming implicit input. rdar://8598427 llvm-svn: 118135
* Modify scheduling itineraries to correct instruction latencies (not operandEvan Cheng2010-11-032-314/+314
| | | | | | latencies) of loads. llvm-svn: 118134
* Print an error as one big string instead of breaking it up.Dan Gohman2010-11-031-3/+3
| | | | llvm-svn: 118130
* Delete unused variables.Dan Gohman2010-11-031-3/+0
| | | | llvm-svn: 118128
* Remove several unhelpful checks for isValid from sys::Path.Dan Gohman2010-11-031-26/+4
| | | | llvm-svn: 118127
* Make sure we're only storing a single bit here.Eric Christopher2010-11-021-2/+9
| | | | llvm-svn: 118126
* per a suggestion by Frits van Bommel, mark all MBlaze Pseudo Chris Lattner2010-11-023-5/+8
| | | | | | | instructions as isCodeGenOnly in the parent class instead of sprinkling it throughout the .td files. llvm-svn: 118125
* Revert r118097 to fix buildbots.Owen Anderson2010-11-022-203/+203
| | | | llvm-svn: 118121
* Completely reject instructions that have an operand in theirChris Lattner2010-11-022-38/+48
| | | | | | | | | | | | ins/outs list that isn't specified by their asmstring. Previously the asmmatcher would just force a 0 register into it, which clearly isn't right. Mark a bunch of ARM instructions that use this as isCodeGenOnly. Some of them are clearly pseudo instructions (like t2TBB) others use a weird hasExtraSrcRegAllocReq thing that will either need to be removed or the asmmatcher will need to be taught about it (someday). llvm-svn: 118119
* Let the -inline-threshold command line argument take precedence over theJakob Stoklund Olesen2010-11-021-1/+2
| | | | | | | | threshold given to createFunctionInliningPass(). Both opt -O3 and clang would silently ignore the -inline-threshold option. llvm-svn: 118117
* Don't try to enforce MAXPATHLEN in sys::Path for Unix. OS's can checkDan Gohman2010-11-021-4/+6
| | | | | | limits on their own. llvm-svn: 118113
* Simplify.Dan Gohman2010-11-021-2/+1
| | | | llvm-svn: 118110
* Fix a copy+pasto.Dan Gohman2010-11-021-1/+2
| | | | llvm-svn: 118106
* Avoid manipulating paths in fixed-sized arrays.Dan Gohman2010-11-021-10/+6
| | | | llvm-svn: 118105
* Obsessive formatting changes. No functionality impact.Bill Wendling2010-11-021-31/+37
| | | | llvm-svn: 118103
* Simplify this code.Dan Gohman2010-11-021-6/+3
| | | | llvm-svn: 118102
* Omit unused parameter name.Bill Wendling2010-11-021-1/+1
| | | | llvm-svn: 118099
* Simplify the EncodeInstruction method now that a lot of the special case stuffBill Wendling2010-11-021-13/+6
| | | | | | is handled with the MC encoder. llvm-svn: 118098
* Since these fields are not exactly equivalent to the encoded field, rename ↵Owen Anderson2010-11-022-203/+203
| | | | | | them to something with semantic meaning. llvm-svn: 118097
* Use '\0' instead of 0 for nul character constants.Dan Gohman2010-11-021-3/+3
| | | | llvm-svn: 118096
* Rename getAddrModeImm12OpValue to getAddrModeImmOpValue and expand it to workBill Wendling2010-11-024-50/+62
| | | | | | | | with immediates up to 16-bits in size. The same logic is applied to other LDR encodings, e.g. VLDR, but which use a different immediate bit width (8-bits in VLDR's case). Removing the "12" allows it to be more generic. llvm-svn: 118094
* Rename encoder methods to match naming convention.Owen Anderson2010-11-023-11/+8
| | | | llvm-svn: 118093
* mark a few codegenonly instructions.Chris Lattner2010-11-022-3/+3
| | | | llvm-svn: 118092
* appendSuffix: don't append a dot when the suffix is empty.Mikhail Glushenkov2010-11-023-24/+15
| | | | | | | Additionally, move the implementation of appendSuffix to Path.cpp: it is platform-independent. llvm-svn: 118089
* Revert r118057, this is better fixed in appendSuffix itself.Mikhail Glushenkov2010-11-021-3/+1
| | | | llvm-svn: 118088
* Provide correct encodings for the remaining vst variants that we currently ↵Owen Anderson2010-11-021-53/+131
| | | | | | generate. llvm-svn: 118087
* Eliminate some temporary std::strings.Dan Gohman2010-11-021-4/+4
| | | | llvm-svn: 118086
* Tentative encodings for the "single element from one lane" variant of vst1.Owen Anderson2010-11-021-14/+32
| | | | llvm-svn: 118084
* Add correct encodings for basic variants for vst3 and vst4.Owen Anderson2010-11-021-37/+47
| | | | llvm-svn: 118082
* Do relaxations with FT_Org fragments. Fixes the FIXME:Rafael Espindola2010-11-021-18/+24
| | | | | | | | | // FIXME: We should compute this sooner, we don't want to recurse here, and // we would like to be more functional. In MCAssembler::ComputeFragmentSize. llvm-svn: 118080
* Add NEON VST1-lane instructions. Partial fix for Radar 8599955.Bob Wilson2010-11-025-4/+80
| | | | llvm-svn: 118069
* Add correct encodings for the basic variants for vst2.Owen Anderson2010-11-021-30/+40
| | | | llvm-svn: 118068
* Add correct encodings for the basic form of vst1.Owen Anderson2010-11-021-54/+74
| | | | llvm-svn: 118067
* Micro-optimize.Dan Gohman2010-11-021-1/+1
| | | | llvm-svn: 118058
* Don't append a dot on platforms which don't use exe suffixes.Dan Gohman2010-11-021-1/+3
| | | | llvm-svn: 118057
* llvmc: Fix tool finding logic.Mikhail Glushenkov2010-11-021-8/+8
| | | | llvm-svn: 118056
* Factor out a common encoding class for loads and stores with a lane parameter.Owen Anderson2010-11-022-22/+18
| | | | llvm-svn: 118055
* Fix DIType verifier. The element 3 is DIFile now.Devang Patel2010-11-021-3/+4
| | | | llvm-svn: 118054
* Add correct encodings for the rest of the vld instructions that we generate.Owen Anderson2010-11-022-74/+182
| | | | llvm-svn: 118053
* GetDLLSuffix: Remove the leading dot from LTDL_SHLIB_EXT.Mikhail Glushenkov2010-11-022-2/+2
| | | | | | This allows using GetDLLSuffix() with appendSuffix(). llvm-svn: 118051
* Trailing whitespace.Mikhail Glushenkov2010-11-021-2/+2
| | | | llvm-svn: 118050
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