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* [LoopInterchange] Allow some loops with PHI nodes in the exit block.Florian Hahn2018-04-271-23/+48
| | | | | | | | | | | | | | | | | | | | We currently support LCSSA PHI nodes in the outer loop exit, if their incoming values do not come from the outer loop latch or if the outer loop latch has a single predecessor. In that case, the outer loop latch will be executed only if the inner loop gets executed. If we have multiple predecessors for the outer loop latch, it may be executed even if the inner loop does not get executed. This is a first step to support the case described in https://bugs.llvm.org/show_bug.cgi?id=30472 Reviewers: efriedma, karthikthecool, mcrosier Reviewed By: efriedma Differential Revision: https://reviews.llvm.org/D43237 llvm-svn: 331037
* [AArch64] Codegen for v8.2A dot product intrinsicsOliver Stannard2018-04-272-13/+39
| | | | | | | | | This adds IR intrinsics for the AArch64 dot-product instructions introduced in v8.2-A. Differential revisioon: https://reviews.llvm.org/D46107 llvm-svn: 331036
* [NVPTX] Turn on Loop/SLP vectorizationBenjamin Kramer2018-04-271-0/+12
| | | | | | | | | | | | | | | | | | | | Since PTX has grown a <2 x half> datatype vectorization has become more important. The late LoadStoreVectorizer intentionally only does loads and stores, but now arithmetic has to be vectorized for optimal throughput too. This is still very limited, SLP vectorization happily creates <2 x half> if it's a legal type but there's still a lot of register moving happening to get that fed into a vectorized store. Overall it's a small performance win by reducing the amount of arithmetic instructions. I haven't really checked what the loop vectorizer does to PTX code, the cost model there might need some more tweaks. I didn't see it causing harm though. Differential Revision: https://reviews.llvm.org/D46130 llvm-svn: 331035
* [X86] Replace some system instruction instregex single matches with instrs ↵Simon Pilgrim2018-04-277-85/+60
| | | | | | entry. NFCI. llvm-svn: 331034
* [mips] Fix how compiler fuse instructions to fmadd/fmsubAleksandar Beserminji2018-04-275-9/+30
| | | | | | | | | | This patch makes compiler does not fuse fmul and fadd/fsub into fmadd/fmsub by default. Instead, -fp-contract=fast option can be used when such behavior is desired. Differential Revision: https://reviews.llvm.org/D46057 llvm-svn: 331033
* [ARM] Codegen for v8.2A dot product intrinsicsOliver Stannard2018-04-271-26/+48
| | | | | | | | | This adds IR intrinsics for the ARM dot-product instructions introduced in v8.2-A. Differential revision: https://reviews.llvm.org/D46106 llvm-svn: 331032
* [ARM] Enable misched for R52.David Green2018-04-271-0/+1
| | | | | | | | | Back when the R52 schedule was added in rL286949, there was no way to enable machine schedules in ARM for specific cores. Since then a target feature has been added. This enables the feature for R52, removing the need to manually specify compiler flags. llvm-svn: 331027
* [IR] Do not assume that function pointers are alignedMikhail Maltsev2018-04-271-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: The value tracking analysis uses function alignment to infer that the least significant bits of function pointers are known to be zero. Unfortunately, this is not correct for ARM targets: the least significant bit of a function pointer stores the ARM/Thumb state information (i.e., the LSB is set for Thumb functions and cleared for ARM functions). The original approach (https://reviews.llvm.org/D44781) introduced a new field for function pointer alignment in the DataLayout structure to address this. But it seems unlikely that optimizations based on function pointer alignment would bring much benefit in practice to justify the additional maintenance burden, so this patch simply assumes that function pointer alignment is always unknown. Reviewers: javed.absar, efriedma Reviewed By: efriedma Subscribers: kristof.beyls, llvm-commits, hfinkel, rogfer01 Differential Revision: https://reviews.llvm.org/D46110 llvm-svn: 331025
* [mips] Add support for Virtualization ASEPetar Jovanovic2018-04-2713-24/+357
| | | | | | | | | | | | | | | | | | | This includes Instructions: tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr, hypcall mfgc0, mtgc0, mfhgc0, mthgc0, dmfgc0, dmtgc0, Assembler directives: .set virt, .set novirt, .module virt, .module novirt Attribute: virt .MIPS.abiflags: VZ (0x100) Patch by Vladimir Stefanovic. Differential Revision: https://reviews.llvm.org/D44905 llvm-svn: 331024
* [SCEV] Add trivial case handling for umin utilities. NFC.Serguei Katkov2018-04-271-2/+11
| | | | | | | | | Reviewers: sanjoy, mkazantsev Reviewed By: mkazantsev Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D46175 llvm-svn: 331022
* [SCEV] Introduce bulk umin creation utilitiesSerguei Katkov2018-04-271-19/+45
| | | | | | | | | | | | | | | | Add new umin creation method which accepts a list of operands. SCEV does not represents umin which is required in getExact, so it transforms umin to umax with not. As a result the transformation of tree of max to max with several operands does not work. We just use the new introduced method for creation umin from several operands. Reviewers: sanjoy, mkazantsev Reviewed By: sanjoy Subscribers: javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D46047 llvm-svn: 331015
* Revert "[SimplifyLibcalls] Replace locked IO with unlocked IO"Matt Morehouse2018-04-273-257/+20
| | | | | | This reverts r331002 due to sanitizer bot breakage. llvm-svn: 331011
* [LowerTypeTests] Mark .cfi.jumptable nounwind.Eli Friedman2018-04-271-0/+2
| | | | | | | | | It doesn't unwind, and the wrong marking leads to the creation of an .eh_frame section when it isn't necessary. Differential Revision: https://reviews.llvm.org/D46082 llvm-svn: 331008
* [MachineOutliner] Don't outline from functions with a section marking.Eli Friedman2018-04-271-0/+7
| | | | | | | | | | | | | | The program might have unusual expectations for functions; for example, the Linux kernel's build system warns if it finds references from .text to .init.data. I'm not sure this is something we actually want to make any guarantees about (there isn't any explicit rule that would disallow outlining in this case), but we might want to be conservative anyway. Differential Revision: https://reviews.llvm.org/D46091 llvm-svn: 331007
* typoSam Clegg2018-04-271-2/+3
| | | | llvm-svn: 331006
* [WebAssembly] Section symbols must have local bindingSam Clegg2018-04-272-1/+5
| | | | | | | | | | Summary: Also test for symbols information in test/MC/WebAssembly/debug-info.ll. Subscribers: jfb, dschuff, jgravelle-google, aheejin, sunfish, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D46160 llvm-svn: 331005
* [SimplifyLibcalls] Replace locked IO with unlocked IODavid Bolvansky2018-04-263-20/+257
| | | | | | | | | | | | Summary: If file stream arg is not captured and source is fopen, we could replace IO calls by unlocked IO ("_unlocked" function variants) to gain better speed, Reviewers: efriedma, RKSimon, spatel, sanjoy, hfinkel, majnemer Subscribers: lebedev.ri, llvm-commits Differential Revision: https://reviews.llvm.org/D45736 llvm-svn: 331002
* [x86] Revert r330322 (& r330323): Lowering x86 adds/addus/subs/subus intrinsicsChandler Carruth2018-04-263-193/+42
| | | | | | | | The LLVM commit introduces a crash in LLVM's instruction selection. I filed http://llvm.org/PR37260 with the test case. llvm-svn: 330997
* Revert "Fix a bug that prevents global variables from having a DW_OP_deref."Adrian Prantl2018-04-261-3/+2
| | | | | | This reverts commit r3309704 while investigating bot breakage. llvm-svn: 330993
* [InstCombine] Simplify Add with remainder expressions as operands.Sanjoy Das2018-04-262-0/+116
| | | | | | | | | | | | | | | | | | | | | Summary: Simplify integer add expression X % C0 + (( X / C0 ) % C1) * C0 to X % (C0 * C1). This is a common pattern seen in code generated by the XLA GPU backend. Add test cases for this new optimization. Patch by Bixia Zheng! Reviewers: sanjoy Reviewed By: sanjoy Subscribers: efriedma, craig.topper, lebedev.ri, llvm-commits, jlebar Differential Revision: https://reviews.llvm.org/D45976 llvm-svn: 330992
* [GlobalISel] Reporting rules covered as part of the InstructionSelect's ↵Roman Tereshin2018-04-262-1/+12
| | | | | | | | | | | | | debug-only printing The main goal of this change is to make it much easier to track which rules are actually covered by Testgen'erated regression tests. Reviewers: aemerson, dsanders Differential Revision: https://reviews.llvm.org/D46095 llvm-svn: 330988
* [mips] Accept 32-bit offsets for lb and lbu commandsSimon Atanasyan2018-04-262-2/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | `lb` and `lbu` commands accepts 16-bit signed offsets. But GAS accepts larger offsets for these commands. If an offset does not fit in 16-bit range, `lb` command is translated into lui/lb or lui/addu/lb series. It's interesting that initially LLVM assembler supported this feature, but later it was broken. This patch restores support for 32-bit offsets. It replaces `mem_simm16` operand for `LB` and `LBu` definitions by the new `mem_simmptr` operand. This operand is intended to check that offset fits to the same size as using for pointers. Later we will be able to extend this rule and accepts 64-bit offsets when it is possible. Some issues remain: - The regression also affects LD, SD, LH, LHU commands. I'm going to fix them by a separate patch. - GAS accepts any 32-bit values as an offset. Now LLVM accepts signed 16-bit values and this patch extends the range to signed 32-bit offsets. In other words, the following code accepted by GAS and still triggers an error by LLVM: ``` lb $4, 0x80000004 # gas lui a0, 0x8000 lb a0, 4(a0) ``` - In case of 64-bit pointers GAS accepts a 64-bit offset and translates it to the li/dsll/lb series of commands. LLVM still rejects it. Probably this feature has never been implemented in LLVM. This issue is for a separate patch. ``` lb $4, 0x800000001 # gas li a0, 0x8000 dsll a0, a0, 0x14 lb a0, 4(a0) ``` Differential Revision: https://reviews.llvm.org/D45020 llvm-svn: 330983
* [WebAssembly] Write DWARF data into wasm object fileSam Clegg2018-04-264-27/+230
| | | | | | | | | | | - Writes ".debug_XXX" into corresponding custom sections. - Writes relocation records into "reloc.debug_XXX" sections. Patch by Yury Delendik! Differential Revision: https://reviews.llvm.org/D44184 llvm-svn: 330982
* DAG: Fix not legalizing vector fcanonicalizesMatt Arsenault2018-04-262-0/+2
| | | | | | If an fcanoncialize was done on a vector type that was legal, llvm-svn: 330981
* AMDGPU: Extend extract_vector_elt fneg combine to fabsMatt Arsenault2018-04-261-2/+3
| | | | | | Fixes a regression in a future commit. llvm-svn: 330980
* AMDGPU: Consolidate SubtargetPredicate definitionsMatt Arsenault2018-04-262-7/+7
| | | | llvm-svn: 330979
* [AArch64] Fix scavenged spill slot base when stack realignment required.Geoff Berry2018-04-261-2/+10
| | | | | | | | | | | | | | | | | | Summary: Use the FP for scavenged spill slot accesses to prevent corruption of the callee-save region when the SP is re-aligned. Based on problem and patch reported by @paulwalker-arm This is an alternative to solution proposed in D45770 Reviewers: t.p.northover, paulwalker-arm, thegameg, javed.absar Subscribers: qcolombet, mcrosier, paulwalker-arm, kristof.beyls, rengolin, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D46063 llvm-svn: 330976
* Fix a bug that prevents global variables from having a DW_OP_deref.Adrian Prantl2018-04-261-2/+3
| | | | | | | | | | | For local variables the first DW_OP_deref is consumed by turning the location kind into a memeory location, but that only makes sense for values that are in a register to begin with, which cannot happen for global variables that are attached to a symbol. rdar://problem/39741860 llvm-svn: 330970
* [WebAssembly] Add version to object file metadataSam Clegg2018-04-263-1/+11
| | | | | | | | | | Summary: See https://github.com/WebAssembly/tool-conventions/issues/54 Subscribers: jfb, dschuff, jgravelle-google, aheejin, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D46069 llvm-svn: 330969
* [GlobalMerge] Fix a typoHaicheng Wu2018-04-261-1/+1
| | | | | | now => know llvm-svn: 330965
* Revert "Enable EliminateAvailableExternally pass for -O1"Vlad Tsyrklevich2018-04-261-1/+1
| | | | | | This reverts commit r330961 because it breaks a handful of clang tests. llvm-svn: 330964
* Update stale comment in AsmWriter.cppVlad Tsyrklevich2018-04-261-1/+3
| | | | | | | | | | | | | | | | | | Summary: The old comment referred to llvm/IR/Writer.h which doesn't longer exist. This patch replaces it with an up-to-date description of AsmWriter library. Patch by Alex Yursha. Reviewers: gribozavr, vlad.tsyrklevich Reviewed By: vlad.tsyrklevich Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45895 llvm-svn: 330962
* Enable EliminateAvailableExternally pass for -O1Vlad Tsyrklevich2018-04-261-1/+1
| | | | | | | | | | | | | | | | | | Summary: Follow-up to D43690, the EliminateAvailableExternally pass currently runs under -O0 and -O2 and up. Under -O1 we would still want to drop available_externally symbols to reduce space without inlining having run. Reviewers: tejohnson Reviewed By: tejohnson Subscribers: mehdi_amini, llvm-commits, kcc Differential Revision: https://reviews.llvm.org/D46093 llvm-svn: 330961
* [WebAssembly] Implement getRelocationValueString()Sam Clegg2018-04-261-4/+8
| | | | | | | | And use it in llvm-objdump. Differential Revision: https://reviews.llvm.org/D46092 llvm-svn: 330957
* [AMDGPU][Waitcnt] As of gfx7, VMEM operations do not increment the export ↵Mark Searles2018-04-262-1/+5
| | | | | | | | counter and the input registers are available in the next instruction; update the waitcnt pass to take this into account. Differential Revision: https://reviews.llvm.org/D46067 llvm-svn: 330954
* [mips] Correct the definitions of some control instructionsSimon Dardis2018-04-263-39/+36
| | | | | | | | | | | | | | Correct the definitions of ei, di, eret, deret, wait, syscall and break. Also provide microMIPS specific aliases to match the MIPS aliases. Additionally correct the definition of the wait instruction so that it is present in the instruction mapping tables. Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D45939 llvm-svn: 330952
* [DAGCombiner] limit ftrunc optimizations with function attributeSanjay Patel2018-04-261-0/+8
| | | | | | | | | | As noted, the attribute name is subject to change once we have the clang side implemented, but it's clear that we need some kind of attribute-based predication here based on the discussion for: rL330437 llvm-svn: 330951
* [RISCV] Implement isLoadFromStackSlot and isStoreToStackSlotAlex Bradbury2018-04-262-0/+54
| | | | | | | | | This causes some slight shuffling but no meaningful codegen differences on the corpus I used for testing, but it has a larger impact when combined with e.g. rematerialisation. Regardless, it makes sense to report as accurate target-specific information as possible. llvm-svn: 330949
* [NVPTX] Make the legalizer expand shufflevector of <2 x half>Benjamin Kramer2018-04-261-0/+1
| | | | | | | | | | There's no direct instruction for this, but it's trivially implemented with two movs. Without this the code generator just dies when encountering a shufflevector. Differential Revision: https://reviews.llvm.org/D46116 llvm-svn: 330948
* [DAGCombiner] refactor FP->int->FP folds; NFCSanjay Patel2018-04-261-16/+26
| | | | | | | | | | | | As discussed in the post-review comments for rL330437, we need to guard this fold to allow existing code to keep working with the undefined behavior that they've come to rely on. That would mean duplicating more code than we already have, so let's fix that first. llvm-svn: 330947
* [RISCV] Implement isZextFreeAlex Bradbury2018-04-262-0/+15
| | | | | | | This returns true for 8-bit and 16-bit loads, allowing LBU/LHU to be selected and avoiding unnecessary masks. llvm-svn: 330943
* [TTI, AArch64] Add transpose shuffle kindMatthew Simpson2018-04-263-10/+103
| | | | | | | | | | | | | | This patch adds a new shuffle kind useful for transposing a 2xn matrix. These transpose shuffle masks read corresponding even- or odd-numbered vector elements from two n-dimensional source vectors and write each result into consecutive elements of an n-dimensional destination vector. The transpose shuffle kind is meant to model the TRN1 and TRN2 AArch64 instructions. As such, this patch also considers transpose shuffles in the AArch64 implementation of getShuffleCost. Differential Revision: https://reviews.llvm.org/D45982 llvm-svn: 330941
* [RISCV] Implement isTruncateFreeAlex Bradbury2018-04-262-0/+22
| | | | | | Adapted from ARM's implementation introduced in r313533 and r314280. llvm-svn: 330940
* [X86] Fix Update Kill Register in Avoid SFB Pass - Bug 37153Lama Saba2018-04-261-19/+29
| | | | | | | Differential Revision: https://reviews.llvm.org/D45823 Change-Id: Icf6f34f6babc3cb2ff5292fde003472473037a71 llvm-svn: 330939
* [RISCV] Implement isLegalICmpImmediateAlex Bradbury2018-04-262-0/+5
| | | | | | | | I'm unable to construct a representative test case that demonstrates the advantage, but it seems sensible to report accurate target-specific information regardless. llvm-svn: 330938
* [RISCV] Implement isLegalAddImmediateAlex Bradbury2018-04-262-0/+5
| | | | | | | This causes a trivial improvement in the recently added lsr-legaladdimm.ll test case. llvm-svn: 330937
* [AArch64][SVE] Enable DiagnosticPredicates for SVE LD1 instructions.Sander de Smalen2018-04-261-14/+27
| | | | | | | | | | | | | | | | | | | | This patch extends the PredicateMethod of AsmOperands used in SVE's LD1 instructions with a DiagnosticPredicate. This makes them 'context sensitive' to the operand that has been parsed and tells the user to use the right register (with expected shift/extend), rather than telling the immediate is out of range when it actually parsed a register. Patch [2/2] in a series to improve assembler diagnostics for SVE: - Patch [1/2]: https://reviews.llvm.org/D45879 - Patch [2/2]: https://reviews.llvm.org/D45880 Reviewers: olista01, stoklund, craig.topper, mcrosier, rengolin, echristo, fhahn, SjoerdMeijer, evandro, javed.absar Reviewed By: fhahn Differential Revision: https://reviews.llvm.org/D45880 llvm-svn: 330934
* [NVPTX] Deduplicate code. No functionality change.Benjamin Kramer2018-04-261-18/+6
| | | | llvm-svn: 330933
* [RISCV] Implement isLegalAddressingMode for RISC-VAlex Bradbury2018-04-262-0/+30
| | | | | | | | | | | | This has no impact on codegen for the current RISC-V unit tests or my small benchmark set and very minor changes in a few programs in the GCC torture suite. Based on this, I haven't been able to produce a representative test program that demonstrates a benefit from isLegalAddressingMode. I'm committing the patch anyway, on the basis that presenting accurate information to the target-independent code is preferable to relying on incorrect generic assumptions. llvm-svn: 330932
* [LoopInterchange] Ignore debug intrinsics during legality checks.Florian Hahn2018-04-261-3/+3
| | | | | | | | | | | | Reviewers: aprantl, mcrosier, karthikthecool Reviewed By: aprantl Subscribers: mattd, vsk, #debug-info, llvm-commits Differential Revision: https://reviews.llvm.org/D45379 llvm-svn: 330931
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