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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2018-04-26 19:21:37 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2018-04-26 19:21:37 +0000 |
| commit | 540512c29719dc98429961c38fa882bcfef1de40 (patch) | |
| tree | a4811c8c4b416f396e05b06939022358ed48bd36 /llvm/lib | |
| parent | fcc5ba46b796eaab5d218321e9cb8a76c18811ac (diff) | |
| download | bcm5719-llvm-540512c29719dc98429961c38fa882bcfef1de40.tar.gz bcm5719-llvm-540512c29719dc98429961c38fa882bcfef1de40.zip | |
DAG: Fix not legalizing vector fcanonicalizes
If an fcanoncialize was done on a vector type that was legal,
llvm-svn: 330981
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 1 |
2 files changed, 2 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp index f8c2db01f0b..a481acd07ca 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp @@ -366,6 +366,7 @@ SDValue VectorLegalizer::LegalizeOp(SDValue Op) { case ISD::UMAX: case ISD::SMUL_LOHI: case ISD::UMUL_LOHI: + case ISD::FCANONICALIZE: QueryType = Node->getValueType(0); break; case ISD::FP_ROUND_INREG: diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 0d71bdd269a..925fdce757a 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -479,6 +479,7 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM, setOperationAction(ISD::FMA, MVT::v2f16, Legal); setOperationAction(ISD::FMINNUM, MVT::v2f16, Legal); setOperationAction(ISD::FMAXNUM, MVT::v2f16, Legal); + setOperationAction(ISD::FCANONICALIZE, MVT::v2f16, Legal); // This isn't really legal, but this avoids the legalizer unrolling it (and // allows matching fneg (fabs x) patterns) |
