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* [PM] Switch the downward invalidation to be incremental where only theChandler Carruth2013-11-221-11/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | one function's analyses are invalidated at a time. Also switch the preservation of the proxy to *fully* preserve the lower (function) analyses. Combined, this gets both upward and downward analysis invalidation to a point I'm happy with: - A function pass invalidates its function analyses, and its parent's module analyses. - A module pass invalidates all of its functions' analyses including the set of which functions are in the module. - A function pass can preserve a module analysis pass. - If all function passes preserve a module analysis pass, that preservation persists. If any doesn't the module analysis is invalidated. - A module pass can opt into managing *all* function analysis invalidation itself or *none*. - The conservative default is none, and the proxy takes the maximally conservative approach that works even if the set of functions has changed. - If a module pass opts into managing function analysis invalidation it has to propagate the invalidation itself, the proxy just does nothing. The only thing really missing is a way to query for a cached analysis or nothing at all. With this, function passes can more safely request a cached module analysis pass without fear of it accidentally running part way through. llvm-svn: 195519
* R600/SI: Fixing handling of condition codesTom Stellard2013-11-224-76/+98
| | | | | | | | We were ignoring the ordered/onordered bits and also the signed/unsigned bits of condition codes when lowering the DAG to MachineInstrs. NOTE: This is a candidate for the 3.4 branch. llvm-svn: 195514
* llvm-cov: Split entry blocks in GCNOProfiling.cpp.Yuchen Wu2013-11-221-0/+3
| | | | | | | | | | | | | gcov expects every function to contain an entry block that unconditionally branches into the next block. clang does not implement basic blocks in this manner, so gcov did not output correct branch info if the entry block branched to multiple blocks. This change splits every function's entry block into an empty block and a block with the rest of the instructions. The instrumentation code will take care of the rest. llvm-svn: 195513
* Debug Info: move StripDebugInfo from StripSymbols.cpp to DebugInfo.cpp.Manman Ren2013-11-222-51/+52
| | | | | | | | | | We can share the implementation between StripSymbols and dropping debug info for metadata versions that do not match. Also update the comments to match the implementation. A follow-on patch will drop the "Debug Info Version" module flag in StripDebugInfo. llvm-svn: 195505
* X86: Perform integer comparisons at i32 or larger.Jim Grosbach2013-11-221-0/+29
| | | | | | | | | | | | | | | Utilizing the 8 and 16 bit comparison instructions, even when an input can be folded into the comparison instruction itself, is typically not worth it. There are too many partial register stalls as a result, leading to significant slowdowns. By always performing comparisons on at least 32-bit registers, performance of the calculation chain leading to the comparison improves. Continue to use the smaller comparisons when minimizing size, as that allows better folding of loads into the comparison instructions. rdar://15386341 llvm-svn: 195496
* StructurizeCFG: Fix verification failure with some loops.Matt Arsenault2013-11-221-0/+14
| | | | | | | | | If the beginning of the loop was also the entry block of the function, branches were inserted to the entry block which isn't allowed. If this occurs, create a new dummy function entry block that branches to the start of the loop. llvm-svn: 195493
* StructurizeCFG: Fix inverting a branch on an argumentMatt Arsenault2013-11-221-11/+22
| | | | llvm-svn: 195492
* Teach ISel not to optimize 'optnone' functions (revised).Paul Robinson2013-11-222-0/+49
| | | | | | | | | | | | | Improvements over r195317: - Set/restore EnableFastISel flag instead of just running FastISel within SelectAllBasicBlocks; the flag is checked in various places, and FastISel won't run properly if those places don't do the right thing. - Test looks for normal ISel versus FastISel behavior, and not something more subtle that doesn't work everywhere. Based on work by Andrea Di Biagio. llvm-svn: 195491
* DEBUG shouldEvict decisionsAndrew Trick2013-11-222-3/+7
| | | | llvm-svn: 195490
* Minor cleanup. EvictionCost ctor was confusing relative to the other costs ↵Andrew Trick2013-11-221-3/+9
| | | | | | floating around in the code. llvm-svn: 195489
* patchpoint: factor SD builder code for live vars. Plain stackmap also ↵Andrew Trick2013-11-221-13/+19
| | | | | | optimizes Constant values now. llvm-svn: 195488
* patchpoint: eliminate hard coded operand indices.Andrew Trick2013-11-221-13/+19
| | | | llvm-svn: 195487
* Add a fixed version of r195470 back.Rafael Espindola2013-11-221-17/+37
| | | | | | | | | | | | | | | | The fix is simply to use CurI instead of I when handling aliases to avoid accessing a invalid iterator. original message: Convert linkonce* to weak* instead of strong. Also refactor the logic into a helper function. This is an important improve on mingw where the linker complains about mixed weak and strong symbols. Converting to weak ensures that the symbol is not dropped, but keeps in a comdat, making the linker happy. llvm-svn: 195477
* Fix PR18014Michael Liao2013-11-221-0/+9
| | | | | | | - When simplifying the mask generation for BLEND, check whether that mask is also consumed by other non-BLEND insns. If true, skip that simplification. llvm-svn: 195476
* [SystemZ] Fix TMHH and TMHL usage for z10 with -O0Richard Sandiford2013-11-224-20/+34
| | | | | | | | | | | | I've no idea why I decided to handle TMxx differently from all the other high/low logic operations, but it was a stupid thing to do. The high registers aren't available as separate 32-bit registers on z10, so subreg_h32 can't be used on a GR64 there. I've normally been testing with z196 and with -O3 and so hadn't noticed this until now. llvm-svn: 195473
* Revert "Convert linkonce* to weak* instead of strong."Rafael Espindola2013-11-221-37/+17
| | | | | | | This reverts commit r195470. Debugging failure in some bots. llvm-svn: 195472
* Add a Scalarizer pass.Richard Sandiford2013-11-223-0/+643
| | | | llvm-svn: 195471
* Convert linkonce* to weak* instead of strong.Rafael Espindola2013-11-221-17/+37
| | | | | | | | | Also refactor the logic into a helper function. This is an important improvement on mingw where the linker complains about mixed weak and strong symbols. Converting to weak ensures that the symbol is not dropped, but keeps in a comdat, making the linker happy. llvm-svn: 195470
* SLPVectorizer: Fix whitespace errors.Arnold Schwaighofer2013-11-221-5/+4
| | | | llvm-svn: 195468
* Don't produce tail calls when the caller is x86_thiscallcc.Rafael Espindola2013-11-221-3/+7
| | | | | | The callee will not pop the stack for us. llvm-svn: 195467
* Fix typo in a comment added in r195455.Daniel Sanders2013-11-221-1/+1
| | | | | | Credit to Matheus Almeida for spotting it. llvm-svn: 195456
* [mips][msa] Fix corner case for integer constant splats with undef values.Daniel Sanders2013-11-221-2/+3
| | | | | | | | | | | | | lowerBUILD_VECTOR() was treating integer constant splats as being legal regardless of whether they had undef values. This caused instruction selection failures when the undefs were legalized to zero, making the constant non-splat. Fixed this by requiring HasAnyUndef to be false for a integer constant splat to be legal. If it is true, a new node is generated with the undefs replaced with the necessary values to remain a splat. llvm-svn: 195455
* [PM] Teach the analysis managers to pass themselves as arguments to theChandler Carruth2013-11-221-2/+2
| | | | | | | | | | | | | | run methods of the analysis passes. Also generalizes and re-uses the SFINAE for transformation passes so that users can write an analysis pass and only accept an analysis manager if that is useful to their pass. This completes the plumbing to make an analysis manager available through every pass's run method if desired so that passes no longer need to be constructed around them. llvm-svn: 195451
* Add support for Cortex-A12.Richard Barton2013-11-222-2/+19
| | | | | | Patch by Oliver Stannard! llvm-svn: 195448
* [PM] Fix the analysis templates' usage of IRUnitT.Chandler Carruth2013-11-221-3/+3
| | | | | | | | | | | This is supposed to be the whole type of the IR unit, and so we shouldn't pass a pointer to it but rather the value itself. In turn, we need to provide a 'Module *' as that type argument (for example). This will become more relevant with SCCs or other units which may not be passed as a pointer type, but also brings consistency with the transformation pass templates. llvm-svn: 195445
* [mips][msa] Float vector constants cannot use ldi.[wd] directly. Bitcast ↵Daniel Sanders2013-11-221-1/+3
| | | | | | | | from the appropriate integer vector type. Fixes an instruction selection failure detected by llvm-stress. llvm-svn: 195444
* Revert r195318 as it causes miscompilation (PR18029)Kostya Serebryany2013-11-221-8/+14
| | | | llvm-svn: 195439
* Fix a Cygwin build failure caused by enum values starting with '_', which is ↵Hao Liu2013-11-224-44/+44
| | | | | | | | conflicted with some platform macros. This patch only renames variables, no functional change. llvm-svn: 195432
* Fix the bugs about AArch64 Load/Store vector types and bitcast between i64 ↵Hao Liu2013-11-221-0/+60
| | | | | | | | | and vector types. e.g. "%tmp = load <2 x i64>* %ptr" can't be selected. "%tmp = bitcast i64 %in to <2 x i32>" can't be selected. llvm-svn: 195424
* Revert last change by haoliu because of buildbot failure.Hao Liu2013-11-224-44/+44
| | | | llvm-svn: 195423
* Fix a Cygwin build failure caused by enum values starting with '_', which is ↵Hao Liu2013-11-224-44/+44
| | | | | | | | | conflicted with some platform macros. This solution only renames variables, no functional change. NOTE: This is a candidate for the 3.4 branch. llvm-svn: 195421
* For AArch64 back-end instruction selection, lower Neon_Lowxxx with ↵Jiangning Liu2013-11-221-41/+41
| | | | | | EXTRCT_SUBREG. llvm-svn: 195408
* SLP Vectorizer: Extract cost will only be added once even if the scalar has ↵Yi Jiang2013-11-221-0/+4
| | | | | | multiple external uses. llvm-svn: 195406
* Fix a typo where we were creating <def,kill> operands instead ofLang Hames2013-11-221-1/+2
| | | | | | | | | | <def,dead> ones. Add an assertion to make sure we catch this in the future. Fixes <rdar://problem/15464559>. llvm-svn: 195401
* [PM] Switch analysis managers to be threaded through the run methodsChandler Carruth2013-11-221-9/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | rather than the constructors of passes. This simplifies the APIs of passes significantly and removes an error prone pattern where the *same* manager had to be given to every different layer. With the new API the analysis managers themselves will have to be cross connected with proxy analyses that allow a pass at one layer to query for the analysis manager of another layer. The proxy will both expose a handle to the other layer's manager and it will provide the invalidation hooks to ensure things remain consistent across layers. Finally, the outer-most analysis manager has to be passed to the run method of the outer-most pass manager. The rest of the propagation is automatic. I've used SFINAE again to allow passes to completely disregard the analysis manager if they don't need or want to care. This helps keep simple things simple for users of the new pass manager. Also, the system specifically supports passing a null pointer into the outer-most run method if your pass pipeline neither needs nor wants to deal with analyses. I find this of dubious utility as while some *passes* don't care about analysis, I'm not sure there are any real-world users of the pass manager itself that need to avoid even creating an analysis manager. But it is easy to support, so there we go. Finally I renamed the module proxy for the function analysis manager to the more verbose but less confusing name of FunctionAnalysisManagerModuleProxy. I hate this name, but I have no idea what else to name these things. I'm expecting in the fullness of time to potentially have the complete cross product of types at the proxy layer: {Module,SCC,Function,Loop,Region}AnalysisManager{Module,SCC,Function,Loop,Region}Proxy (except for XAnalysisManagerXProxy which doesn't make any sense) This should make it somewhat easier to do the next phases which is to build the upward proxy and get its invalidation correct, as well as to make the invalidation within the Module -> Function mapping pass be more fine grained so as to invalidate fewer fuction analyses. After all of the proxy analyses are done and the invalidation working, I'll finally be able to start working on the next two fun fronts: how to adapt an existing pass to work in both the legacy pass world and the new one, and building the SCC, Loop, and Region counterparts. Fun times! llvm-svn: 195400
* R600: Implement TargetInstrInfo::isLegalToSplitMBBAt()Tom Stellard2013-11-222-0/+14
| | | | | | | | | | | | Splitting a basic block will create a new ALU clause, so we need to make sure we aren't moving uses of registers that are local to their current clause into a new one. I had a test case for this, but unfortunately unrelated schedule changes invalidated it, and I wasn't been able to come up with another one. NOTE: This is a candidate for the 3.4 branch. llvm-svn: 195399
* SelectionDAG: Optimize expansion of vec_type = BITCAST scalar_typeTom Stellard2013-11-222-10/+41
| | | | | | | | | The legalizer can now do this type of expansion for more type combinations without loading and storing to and from the stack. NOTE: This is a candidate for the 3.4 branch. llvm-svn: 195398
* Split SETCC if VSELECT requires splitting too.Tom Stellard2013-11-222-21/+43
| | | | | | | | | | | | | This patch is a rewrite of the original patch commited in r194542. Instead of relying on the type legalizer to do the splitting for us, we now peform the splitting ourselves in the DAG combiner. This is necessary for the case where the vector mask is a legal type after promotion and still wouldn't require splitting. Patch by: Juergen Ributzka NOTE: This is a candidate for the 3.4 branch. llvm-svn: 195397
* In Dwarf 3 (and Dwarf 2) attributes whose value are offsets into aEric Christopher2013-11-214-52/+92
| | | | | | | | | | | | | | | | | | | | | section use the form DW_FORM_data4 whilst in Dwarf 4 and later they use the form DW_FORM_sec_offset. This patch updates the places where such attributes are generated to use the appropriate form depending on the Dwarf version. The DIE entries affected have the following tags: DW_AT_stmt_list, DW_AT_ranges, DW_AT_location, DW_AT_GNU_pubnames, DW_AT_GNU_pubtypes, DW_AT_GNU_addr_base, DW_AT_GNU_ranges_base It also adds a hidden command line option "--dwarf-version=<uint>" to llc which allows the version of Dwarf to be generated to override what is specified in the metadata; this makes it possible to update existing tests to check the debugging information generated for both Dwarf 4 (the default) and Dwarf 3 using the same metadata. Patch (slightly modified) by Keith Walker! llvm-svn: 195391
* SHLD/SHRD are VectorPath (microcode) instructions known to have poor latency ↵Ekaterina Romanova2013-11-214-18/+53
| | | | | | | | | | on certain architectures. While generating SHLD/SHRD instructions is acceptable when optimizing for size, optimizing for speed on these platforms should be implemented using alternative sequences of instructions composed of add, adc, shr, shl, or and lea which are directPath instructions. These alternative instructions not only have a lower latency but they also increase the decode bandwidth by allowing simultaneous decoding of a third directPath instruction. AMD's processors family K7, K8, K10, K12, K15 and K16 are known to have SHLD/SHRD instructions with very poor latency. Optimization guides for these processors recommend using an alternative sequence of instructions. For these AMD's processors, I disabled folding (or (x << c) | (y >> (64 - c))) when we are not optimizing for size. It might be beneficial to disable this folding for some of the Intel's processors. However, since I couldn't find specific recommendations regarding using SHLD/SHRD instructions on Intel's processors, I haven't disabled this peephole for Intel. llvm-svn: 195383
* Introduce two command-line flags for the instrumentation pass to control ↵Peter Collingbourne2013-11-211-10/+33
| | | | | | | | | | | | | | whether the labels of pointers should be ignored in load and store instructions The new command line flags are -dfsan-ignore-pointer-label-on-store and -dfsan-ignore-pointer-label-on-load. Their default value matches the current labelling scheme. Additionally, the function __dfsan_union_load is marked as readonly. Patch by Lorenzo Martignoni! Differential Revision: http://llvm-reviews.chandlerc.com/D2187 llvm-svn: 195382
* Move member variable up to where the rest of non-DWARF5 variables reside.Eric Christopher2013-11-211-3/+3
| | | | llvm-svn: 195380
* [mips][msa] Fix a corner case in performORCombine() when combining nodes ↵Daniel Sanders2013-11-211-4/+8
| | | | | | | | | | | | | | | into VSELECT. Mask == ~InvMask asserts if the width of Mask and InvMask differ. The combine isn't valid (with two exceptions, see below) if the widths differ so test for this before testing Mask == ~InvMask. In the specific cases of Mask=~0 and InvMask=0, as well as Mask=0 and InvMask=~0, the combine is still valid. However, there are more appropriate combines that could be used in these cases such as folding x & 0 to 0, or x & ~0 to x. llvm-svn: 195364
* [ARM] add basic Cortex-A7 support to LLVM backendArtyom Skrobov2013-11-212-1/+13
| | | | llvm-svn: 195358
* Add support for legalizing SETNE/SETEQ by inverting the condition code and ↵Daniel Sanders2013-11-211-14/+54
| | | | | | | | | | | | | | | | | | | | | | | | | the result of the comparison. Summary: LegalizeSetCCCondCode can now legalize SETEQ and SETNE by returning the inverse condition and requesting that the caller invert the result of the condition. The caller of LegalizeSetCCCondCode must handle the inverted CC, and they do so as follows: SETCC, BR_CC: Invert the result of the SETCC with SelectionDAG::getNOT() SELECT_CC: Swap the true/false operands. This is necessary for MSA which lacks an integer SETNE instruction. Reviewers: resistor CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D2229 llvm-svn: 195355
* [msan] Propagate condition origin in select instruction.Evgeniy Stepanov2013-11-211-5/+12
| | | | llvm-svn: 195349
* [mips][msa/dsp] Only do DSP combines if DSP is enabled.Daniel Sanders2013-11-211-0/+3
| | | | | | Fixes a crash (null pointer dereferenced) when MSA is enabled. llvm-svn: 195343
* Whitespace.NAKAMURA Takumi2013-11-211-1/+1
| | | | llvm-svn: 195341
* Revert r195317 (and r195333), "Teach ISel not to optimize 'optnone' functions."NAKAMURA Takumi2013-11-212-45/+1
| | | | | | | | It broke, at least, i686 target. It is reproducible with "llc -mtriple=i686-unknown". FYI, it didn't appear to add either "-O0" or "-fast-isel". llvm-svn: 195339
* [PM] Widen the interface for invalidate on an analysis result now thatChandler Carruth2013-11-211-7/+15
| | | | | | | | | | | | | | | | | | | it is completely optional, and sink the logic for handling the preserved analysis set into it. This allows us to implement the delegation logic desired in the proxy module analysis for the function analysis manager where if the proxy itself is preserved we assume the set of functions hasn't changed and we do a fine grained invalidation by walking the functions in the module and running the invalidate for them all at the manager level and letting it try to invalidate any passes. This in turn makes it blindingly obvious why we should hoist the invalidate trait and have two collections of results. That allows handling invalidation for almost all analyses without indirect calls and it allows short circuiting when the preserved set is all. llvm-svn: 195338
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