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* [mips][sched] Split IIStore into II_S[BHWD], II_S[WD][LR], and II_SAVEDaniel Sanders2014-01-234-23/+39
| | | | | | No functional change since the InstrItinData's have been duplicated. llvm-svn: 199876
* Add a variable to track whether or not we've used a unique section,Eric Christopher2014-01-2311-26/+27
| | | | | | | | | | | | e.g. linkonce, to TargetMachine and set it when we've done so for ELF targets currently. This involved making TargetMachine non-const in a TLOF use and propagating that change around - I'm open to other ideas. This will be used in a future commit to handle emitting debug information with ranges. llvm-svn: 199871
* fix some spell mistakes around 'ConcatVector' and 'ShuffleVector' in AArch64 ↵Kevin Qin2014-01-232-5/+5
| | | | | | backend. llvm-svn: 199858
* X86Disassembler.cpp: Fix @param introduced in r199804. [-Wdocumentation]NAKAMURA Takumi2014-01-231-1/+0
| | | | llvm-svn: 199855
* [Mips] formatting through clang-formatJack Carter2014-01-221-10/+10
| | | | llvm-svn: 199853
* [Mips] TargetStreamer Support for .set mips16.Jack Carter2014-01-223-3/+49
| | | | | | | | | | This patch updates .set mips16 support which affects the ELF ABI and its flags. In addition the patch uses a common interface for both the MipsTargetSteamer and MipsObjectStreamer that the assembler uses for both ELF and ASCII output for these directives. llvm-svn: 199851
* Revert r162101 and replace it with a solution that works for targets where ↵Owen Anderson2014-01-222-7/+11
| | | | | | | | | | the pointer type is illegal. This is a horrible bit of code. We're calling a simplification routine *in the middle* of type legalization. We tell the simplification routine that it's running after legalization, but some of the types it will encounter will be illegal! The fix is only to invoke the simplification if the types in question were legal, so that none of its invariants will be violated. llvm-svn: 199847
* Revert "R600: Add work-around for the CF stack entry HW bug"Tom Stellard2014-01-225-63/+7
| | | | | | | | | This reverts commit 35b8331cad6eb512a2506adbc394201181da94ba. The -debug-only flag for llc doesn't appear to be available in all build configurations. llvm-svn: 199845
* Provide a dummy section to fix a crash with inline assembly in LTO.Rafael Espindola2014-01-221-1/+26
| | | | | | Fixes pr18508. llvm-svn: 199843
* R600: Add work-around for the CF stack entry HW bugTom Stellard2014-01-225-7/+63
| | | | | | | | | | | | | | | | The CF stack can be corrupted if you use CF_ALU_PUSH_BEFORE, CF_ALU_ELSE_AFTER, CF_ALU_BREAK, or CF_ALU_CONTINUE when the number of sub-entries on the stack is greater than or equal to the stack entry size and sub-entries modulo 4 is either 0 or 3 (on cedar the bug is present when number of sub-entries module 8 is either 7 or 0) We choose to be conservative and always apply the work-around when the number of sub-enries is greater than or equal to the stack entry size, so that we can safely over-allocate the stack when we are unsure of the stack allocation rules. reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 199842
* R600: Add some missing CF instruction definitions to the .td files.Tom Stellard2014-01-221-0/+7
| | | | | reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 199841
* R600: Refactor stack size calculationTom Stellard2014-01-223-36/+157
| | | | | reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 199840
* R600: CF_PUSH is the same on Evergreen and CaymanTom Stellard2014-01-222-4/+5
| | | | | reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 199839
* R600: Add wavefront size property to the subtargets v2Tom Stellard2014-01-224-12/+33
| | | | | | | | v2: - Initialize wavefront size to 0 reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 199838
* R600: Add stack size to .AMDGPUcsdata sectionTom Stellard2014-01-221-4/+10
| | | | | reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 199837
* Handle an addrspacecast case in memcpyoptMatt Arsenault2014-01-221-1/+1
| | | | llvm-svn: 199836
* Get right cost for addrspacecast in cost modelMatt Arsenault2014-01-221-1/+2
| | | | llvm-svn: 199833
* Fix pr18515.Rafael Espindola2014-01-222-14/+18
| | | | | | | | | | | | | My understanding (from reading just the llvm code) is that * most ppc cpus have a "sync n" instruction and an msync alias that is "sync 0". * "book e" cpus instead have a msync instruction and not the more general "sync n" This patch reflects that in the .td files, allowing a single codepath for asm ond obj streamer and incidentelly fixes a crash when EmitRawText was called on a obj streamer. llvm-svn: 199832
* R600: MOVA is vector onlyTom Stellard2014-01-221-1/+1
| | | | llvm-svn: 199827
* R600: Take alignment into account when calculating the stack offsetTom Stellard2014-01-221-4/+11
| | | | llvm-svn: 199826
* R600: Add support for global addresses with constant initializersTom Stellard2014-01-223-15/+108
| | | | llvm-svn: 199825
* R600: Begin private memory at the second GPR.Tom Stellard2014-01-221-1/+4
| | | | | | | This way private memory does not over-write work group information stored in GPRs 0 and 1. llvm-svn: 199824
* R600/SI: Add support for i8 and i16 private loads/storesTom Stellard2014-01-224-11/+141
| | | | llvm-svn: 199823
* Bug 18228 - Fix accepting bitcasts between vectors of pointers with aMatt Arsenault2014-01-221-16/+41
| | | | | | | | | | | | | different number of elements. Bitcasts were passing with vectors of pointers with different number of elements since the number of elements was checking SrcTy->getVectorNumElements() == SrcTy->getVectorNumElements() which isn't helpful. The addrspacecast was also wrong, but that case at least is caught by the verifier. Refactor bitcast and addrspacecast handling in castIsValid to be more readable and fix this problem. llvm-svn: 199821
* Fix inline assembly that switches between ARM and Thumb modesGreg Fitzgerald2014-01-223-9/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch restores the ARM mode if the user's inline assembly does not. In the object streamer, it ensures that instructions following the inline assembly are encoded correctly and that correct mapping symbols are emitted. For the asm streamer, it emits a .arm or .thumb directive. This patch does not ensure that the inline assembly contains the ADR instruction to switch modes at runtime. The problem we need to solve is code like this: int foo(int a, int b) { int r = a + b; asm volatile( ".align 2 \n" ".arm \n" "add r0,r0,r0 \n" : : "r"(r)); return r+1; } If we compile this function in thumb mode then the inline assembly will switch to arm mode. We need to make sure that we switch back to thumb mode after emitting the inline assembly or we will incorrectly encode the instructions that follow (i.e. the assembly instructions for return r+1). Based on patch by David Peixotto Change-Id: Ib57f6d2d78a22afad5de8693fba6230ff56ba48b llvm-svn: 199818
* Remove param doxygen comment for non-existing parameter.Benjamin Kramer2014-01-221-1/+0
| | | | | | Found by -Wdocumentation. llvm-svn: 199814
* Pass the computed magic to createBinary and createObjectFile if available.Rafael Espindola2014-01-222-12/+14
| | | | | | | identify_magic is not free, so we should avoid calling it twice. The argument also makes it cheap for createBinary to just forward to createObjectFile. llvm-svn: 199813
* [x86] Silence unused diReg variable warning in non-asserting buildsDavid Woodhouse2014-01-221-4/+3
| | | | llvm-svn: 199812
* [x86] Fix uninitialized variable warning in translate{Src,Dst}IndexDavid Woodhouse2014-01-221-2/+6
| | | | llvm-svn: 199811
* [x86] Remove now-unused isSrcOp() and isDstOp() from X86AsmParserDavid Woodhouse2014-01-221-30/+0
| | | | llvm-svn: 199810
* [x86] Allow segment and address-size overrides for INS[BWLQ] (PR9385)David Woodhouse2014-01-222-13/+17
| | | | llvm-svn: 199809
* [x86] Allow segment and address-size overrides for OUTS[BWLQ] (PR9385)David Woodhouse2014-01-222-13/+16
| | | | llvm-svn: 199808
* [x86] Allow segment and address-size overrides for MOVS[BWLQ] (PR9385)David Woodhouse2014-01-222-21/+34
| | | | llvm-svn: 199807
* ]x86] Allow segment and address-size overrides for CMPS[BWLQ] (PR9385)David Woodhouse2014-01-225-5/+80
| | | | llvm-svn: 199806
* [x86] Allow address-size overrides for SCAS{8,16,32,64} (PR9385)David Woodhouse2014-01-222-5/+28
| | | | llvm-svn: 199805
* [x86] Allow address-size overrides for STOS[BWLQ] (PR9385)David Woodhouse2014-01-2212-35/+189
| | | | llvm-svn: 199804
* [x86] Allow segment and address-size overrides for LODS[BWLQ] (PR9385)David Woodhouse2014-01-2212-35/+212
| | | | llvm-svn: 199803
* Loop strength reduce: fix function name.Tim Northover2014-01-221-8/+8
| | | | llvm-svn: 199801
* AVX512: combining setcc and zext is wrong on AVX512Elena Demikhovsky2014-01-221-1/+4
| | | | | | because vector compare instruction puts result in mask register. llvm-svn: 199798
* MachineCopyPropagation has special logic for removing COPY instructions. It ↵James Molloy2014-01-221-8/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | will remove plain COPYs using eraseFromParent(), but if the COPY has imp-defs/imp-uses it will convert it to a KILL, to keep the imp-def around. This actually totally breaks and causes the machine verifier to cry in several cases, one of which being: %RAX<def> = COPY %RCX<kill> %ECX<def> = COPY %EAX<kill>, %RAX<imp-use,kill> These subregister copies are together identified as noops, so are both removed. However, the second one as it has an imp-use gets converted into a kill: %ECX<def> = KILL %EAX<kill>, %RAX<imp-use,kill> As the original COPY has been removed, the verifier goes into tears at the use of undefined EAX and RAX. There are several hacky solutions to this hacky problem (which is all to do with imp-use/def weirdnesses), but the least hacky I've come up with is to *always* remove COPYs by converting to KILLs. KILLs are no-ops to the code generator so the generated code doesn't change (which is why they were partially used in the first place), but using them also keeps the def/use and imp-def/imp-use chains alive: %RAX<def> = KILL %RCX<kill> %ECX<def> = KILL %EAX<kill>, %RAX<imp-use,kill> The patch passes all test cases including the ones that check the removal of MOVs in this circumstance, along with an extra test I added to check subregister behaviour (which made the machine verifier fall over before my patch). The patch also adds some DEBUG() statements because the file hadn't got any. llvm-svn: 199797
* [AArch64 NEON] Try to generate CONCAT_VECTOR when lowering BUILD_VECTOR or ↵Kevin Qin2014-01-222-29/+90
| | | | | | SHUFFLE_VECTOR. llvm-svn: 199791
* Reformat a loop for basic hygeine. Self review.Andrew Trick2014-01-221-5/+5
| | | | llvm-svn: 199788
* [Sparc] Add support for inline assembly constraints which specify registers ↵Venkatraman Govindaraju2014-01-221-0/+20
| | | | | | by their aliases. llvm-svn: 199786
* Fix typoMatt Arsenault2014-01-221-1/+1
| | | | llvm-svn: 199784
* [Sparc] Add support for inline assembly constraint 'I'. Venkatraman Govindaraju2014-01-222-0/+67
| | | | llvm-svn: 199781
* Change createObjectFile to return an ErrorOr.Rafael Espindola2014-01-224-18/+17
| | | | llvm-svn: 199776
* [Sparc] Do not add PC to _GLOBAL_OFFSET_TABLE_ address to access GOT in ↵Venkatraman Govindaraju2014-01-221-30/+94
| | | | | | | | absolute code. Fixes PR#18521 llvm-svn: 199775
* [SROA] Fix a bug which could cause the common type finding to returnChandler Carruth2014-01-211-22/+19
| | | | | | | | | | | | | inconsistent results for different orderings of alloca slices. The fundamental issue is that it is just always a mistake to return early from this function. There is no effective early exit to leverage. This patch stops trynig to do so and simplifies the code a bit as a consequence. Original diagnosis and patch by James Molloy with some name tweaks by me in part reflecting feedback from Duncan Smith on the mailing list. llvm-svn: 199771
* Be a bit more consistent about using ErrorOr when constructing Binary objects.Rafael Espindola2014-01-217-75/+74
| | | | | | | | | | | | | | | | | | | | | | | The constructors of classes deriving from Binary normally take an error_code as an argument to the constructor. My original intent was to change them to have a trivial constructor and move the initial parsing logic to a static method returning an ErrorOr. I changed my mind because: * A constructor with an error_code out parameter is extremely convenient from the implementation side. We can incrementally construct the object and give up when we find an error. * It is very efficient when constructing on the stack or when there is no error. The only inefficient case is where heap allocating and an error is found (we have to free the memory). The result is that this is a much smaller patch. It just standardizes the create* helpers to return an ErrorOr. Almost no functionality change: The only difference is that this found that we were trying to read past the end of COFF import library but ignoring the error. llvm-svn: 199770
* CodeGen: Stop treating vectors as aggregatesDuncan P. N. Exon Smith2014-01-211-1/+1
| | | | | | | | | Fix a crash in SjLjEHPrepare::lowerIncomingArguments caused by treating VectorType like an aggregate. It's first-class! <rdar://problem/15854596> llvm-svn: 199768
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