summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
...
* LegalizeIntegerTypes: Reenable the large shift with small amount optimization.Benjamin Kramer2012-02-281-11/+21
| | | | | | | | | | | | | To avoid problems with zero shifts when getting the bits that move between words we use a trick: first shift the by amount-1, then do another shift by one. When amount is 0 (and size 32) we first shift by 31, then by one, instead of by 32. Also fix a latent bug that emitted the low and high words in the wrong order when shifting right. Fixes PR12113. llvm-svn: 151637
* Revert r151623 "Some ARM implementaions, e.g. A-series, does return stack ↵Daniel Dunbar2012-02-2834-214/+77
| | | | | | prediction. ...", it is breaking the Clang build during the Compiler-RT part. llvm-svn: 151630
* Remove stray semi-colon.Daniel Dunbar2012-02-281-1/+1
| | | | llvm-svn: 151629
* Code cleanup following CR by Duncan.Nadav Rotem2012-02-281-5/+3
| | | | llvm-svn: 151627
* Fix a bug in the code that builds SDNodes from vector GEPs.Nadav Rotem2012-02-281-0/+4
| | | | | | | | | | | When the GEP index is a vector of pointers, the code that calculated the size of the element started from the vector type, and not the contained pointer type. As a result, instead of looking at the data element pointed by the vector, this code used the size of the vector. This works for 32bit members (on 32bit systems), but not for other types. Added code to peel the vector type and added a test. llvm-svn: 151626
* remove blanks, and some code formatJia Liu2012-02-2834-156/+156
| | | | llvm-svn: 151625
* Some ARM implementaions, e.g. A-series, does return stack prediction. That is,Evan Cheng2012-02-2834-77/+214
| | | | | | | | | | | | | | | | | the processor keeps a return addresses stack (RAS) which stores the address and the instruction execution state of the instruction after a function-call type branch instruction. Calling a "noreturn" function with normal call instructions (e.g. bl) can corrupt RAS and causes 100% return misprediction so LLVM should use a unconditional branch instead. i.e. mov lr, pc b _foo The "mov lr, pc" is issued in order to get proper backtrace. rdar://8979299 llvm-svn: 151623
* Reverted r152620 - DSE: Shorten memset when a later store overwrites the ↵Pete Cooper2012-02-281-66/+2
| | | | | | start of it. There were all sorts of buildbot issues llvm-svn: 151621
* DSE: Shorten memset when a later store overwrites the start of itPete Cooper2012-02-281-2/+66
| | | | llvm-svn: 151620
* Oops...Don't commit the other stuff..Bill Wendling2012-02-281-44/+29
| | | | llvm-svn: 151618
* Modify comment to reflect the importance of this code.Bill Wendling2012-02-281-29/+44
| | | | llvm-svn: 151617
* Add comments.Akira Hatanaka2012-02-281-0/+4
| | | | llvm-svn: 151615
* Do not reserve $gp as a dedicated global base register if the target ABI is ↵Akira Hatanaka2012-02-281-1/+2
| | | | | | not O32. llvm-svn: 151614
* Add support for floating point base register + offset register addressing modeAkira Hatanaka2012-02-286-4/+91
| | | | | | load and store instructions. llvm-svn: 151611
* Handle regmasks in MachineCSE.Jakob Stoklund Olesen2012-02-281-0/+6
| | | | | | | | Don't attempt to extend physreg live ranges across calls. <rdar://problem/10942095> llvm-svn: 151610
* Handle regmasks in the machine code verifier.Jakob Stoklund Olesen2012-02-281-0/+15
| | | | llvm-svn: 151607
* Enable ARM base pointer when calling functions with large arguments.Jakob Stoklund Olesen2012-02-283-5/+44
| | | | | | | | | | | | | | | | | | When an outgoing call takes more than 2k of arguments on the stack, we don't allocate that call frame in the prolog, but adjust the stack pointer immediately before the call instead. This causes problems with the emergency spill slot because PEI can't track stack pointer adjustments on the second pass, and if the outgoing arguments are too big, SP can't be used to reach the emergency spill slot at all. Work around these problems by ensuring there is a base or frame pointer that can be used to access the emergency spill slot. <rdar://problem/10917166> llvm-svn: 151604
* [Object] Add {begin,end}_dynamic_symbols stubs and implementation for ELF.Michael J. Spencer2012-02-282-0/+19
| | | | | | | | Add -D option to llvm-nm to dump dynamic symbols. Patch by David Meyer. llvm-svn: 151600
* Fix 80-column violation.Chad Rosier2012-02-281-2/+2
| | | | llvm-svn: 151599
* Add back removed code. It still causes LLVM to miscompile. But not having it ↵Bill Wendling2012-02-271-0/+30
| | | | | | breaks other things. llvm-svn: 151594
* This patch adds instruction latencies for the SSE instructionsPreston Gurd2012-02-273-728/+1697
| | | | | | to the instruction scheduler for the Intel Atom. llvm-svn: 151590
* Duncan pointed out that if the alignment isn't explicitly specified, it ↵Eli Friedman2012-02-271-4/+4
| | | | | | defaults to the ABI alignment. Given that, make this code a bit more aggressive in such cases. llvm-svn: 151584
* Delete incorrect reference to inexistent Hexagon architecture manuals.Evandro Menezes2012-02-271-3/+0
| | | | llvm-svn: 151582
* Don't use #if 0. Just remove until I can address this.Bill Wendling2012-02-271-35/+0
| | | | llvm-svn: 151580
* The code that cleans up multiple, isomorphic types has a subtle error thatBill Wendling2012-02-271-3/+7
| | | | | | | manifests itself when building LLVM with LTO. <rdar://problem/10913281> llvm-svn: 151576
* Fix for PR12090: clear def maps of aliases when visiting a copy. e.g.Evan Cheng2012-02-271-0/+5
| | | | | | | | | %S5<def> = COPY %S0<kill> First clear def map of Q1, etc. No small test case available. llvm-svn: 151574
* ARM BL/BLX instruction fixups should use relocations.Jim Grosbach2012-02-278-15/+50
| | | | | | | | | | | | | We on the linker to resolve calls to the appropriate BL/BLX instruction to make interworking function correctly. It uses the symbol in the relocation to do that, so we need to be careful about being too clever. To enable this for ARM mode, split the BL/BLX fixup kind off from the unconditional-branch fixups. rdar://10927209 llvm-svn: 151571
* Teach BasicAA about the LLVM IR rules that allow reading past the end of an ↵Eli Friedman2012-02-271-9/+26
| | | | | | object given sufficient alignment. Fixes PR12098. llvm-svn: 151553
* Reapply r151278 with fixes.Roman Divacky2012-02-271-6/+16
| | | | | | MCize function entry label emission on PowerPC64 properly. llvm-svn: 151547
* Add q suffix aliases for the fistp and fisttp mnemonics.Chad Rosier2012-02-271-0/+2
| | | | | | | rdar://10921670 PR11935 llvm-svn: 151543
* Remove unnecessary template parameters.Akira Hatanaka2012-02-271-15/+13
| | | | llvm-svn: 151540
* Fix instruction predicates that were not set correctly.Akira Hatanaka2012-02-271-8/+10
| | | | llvm-svn: 151538
* Update machine code verifier.Jakob Stoklund Olesen2012-02-271-35/+91
| | | | | | | | | After the SlotIndex slot names were updated, it is possible to apply stricter checks to live intervals. Also treat bundles as bags of operands when checking live intervals. llvm-svn: 151531
* Fix the symbolic operand added for the C disassmbler API for the ARM blKevin Enderby2012-02-271-1/+1
| | | | | | thumb instruction. The PC adjustment is +4 in Thumb mode and +8 in ARM mode. llvm-svn: 151530
* Plog a memleak in GlobalOpt.Benjamin Kramer2012-02-271-1/+1
| | | | | | Found by valgrind. llvm-svn: 151525
* Micro-optimization, no functionality change.Duncan Sands2012-02-271-7/+12
| | | | llvm-svn: 151524
* The value numbering function is recursive, so it is possible for multiple newDuncan Sands2012-02-271-2/+2
| | | | | | | | value numbers to be assigned when calculating any particular value number. Enhance the logic that detects new value numbers to take this into account, for a tiny compile time speedup. Fix a comment typo while there. llvm-svn: 151522
* When performing a conditional branch depending on the value of a comparisonDuncan Sands2012-02-271-4/+62
| | | | | | | | | %cmp (eg: A==B) we already replace %cmp with "true" under the true edge, and with "false" under the false edge. This change enhances this to replace the negated compare (A!=B) with "false" under the true edge and "true" under the false edge. Reported to improve perlbench results by 1%. llvm-svn: 151517
* Remove HexagonGenIntrinsics.inc from Hexagon cmake file. It does not appear ↵Craig Topper2012-02-271-1/+0
| | | | | | in the Makefile and the output it produces isn't used. The Hexagon intrinsics are all in the global Intrinsics.gen. llvm-svn: 151514
* delete useless comment&blankJia Liu2012-02-271-16/+14
| | | | llvm-svn: 151512
* Fix this assert. IP can point to an instruction with strange dominanceRafael Espindola2012-02-271-15/+20
| | | | | | | properties (invoke). Just assert that the instruction we return dominates the insertion point. llvm-svn: 151511
* X86 disassembler support for jcxz, jecxz, and jrcxz. Fixes PR11643. Patch by ↵Craig Topper2012-02-273-3/+9
| | | | | | Kay Tiong Khoo. llvm-svn: 151510
* Don't call dominates on unreachable instructions. Should fix the dragoneggRafael Espindola2012-02-261-2/+6
| | | | | | build. Testcase is still reducing. llvm-svn: 151474
* Default TargetData alignment information for 128-bit floating-point types.Hal Finkel2012-02-261-0/+1
| | | | llvm-svn: 151473
* And update the comment...Rafael Espindola2012-02-261-1/+0
| | | | llvm-svn: 151472
* Enable the assert that got all this dominator work started.Rafael Espindola2012-02-261-1/+1
| | | | llvm-svn: 151471
* Use the DT dominates function in the verifier.Rafael Espindola2012-02-261-72/+55
| | | | llvm-svn: 151470
* Change the implementation of dominates(inst, inst) to one based on what theRafael Espindola2012-02-262-23/+92
| | | | | | | | verifier does. This correctly handles invoke. Thanks to Duncan, Andrew and Chris for the comments. Thanks to Joerg for the early testing. llvm-svn: 151469
* Don't call dominates on unreachable instructions.Rafael Espindola2012-02-261-2/+2
| | | | llvm-svn: 151468
* Reinstate the optimization from r151449 with a fix to not turn 'gep %x' intoNick Lewycky2012-02-261-11/+51
| | | | | | 'gep null' when the icmp predicate is unsigned (or is signed without inbounds). llvm-svn: 151467
OpenPOWER on IntegriCloud