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* [DAG][X86] Convert isNegatibleForFree/GetNegatedExpression to a target hook ↵Simon Pilgrim2019-10-012-276/+272
| | | | | | | | | | | | | | | | (PR42863) This patch converts the DAGCombine isNegatibleForFree/GetNegatedExpression into overridable TLI hooks. The intention is to let us extend existing FNEG combines to work more generally with negatible float ops, allowing it work with target specific combines and opcodes (e.g. X86's FMA variants). Unlike the SimplifyDemandedBits, we can't just handle target nodes through a Target callback, we need to do this as an override to allow targets to handle generic opcodes as well. This does mean that the target implementations has to duplicate some checks (recursion depth etc.). Partial reversion of rL372756 - I've identified the infinite loop issue inside the X86 override but haven't fixed it yet so I've only (re)committed the common TargetLowering refactoring part of the patch. Differential Revision: https://reviews.llvm.org/D67557 llvm-svn: 373343
* [Dominators][CodeGen] Add MachinePostDominatorTree verificationJakub Kuderski2019-10-013-8/+17
| | | | | | | | | | | | | | | | | | | | | Summary: This patch implements Machine PostDominator Tree verification and ensures that the verification doesn't fail the in-tree tests. MPDT verification can be enabled using `verify-machine-dom-info` -- the same flag used by Machine Dominator Tree verification. Flipping the flag revealed that MachineSink falsely claimed to preserve CFG and MDT/MPDT. This patch fixes that. Reviewers: arsenm, hliao, rampitec, vpykhtin, grosser Reviewed By: hliao Subscribers: wdng, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68235 llvm-svn: 373341
* Revert rL349624 : Let TableGen write output only if it changed, instead of ↵Simon Pilgrim2019-10-011-24/+8
| | | | | | | | | | doing so in cmake, attempt 2 Differential Revision: https://reviews.llvm.org/D55842 ----------------- As discussed on PR43385 this is causing Visual Studio msbuilds to perpetually rebuild all tablegen generated files llvm-svn: 373338
* Revert [InstCombine] sprintf(dest, "%s", str) -> memccpy(dest, str, 0, MAX)David Bolvansky2019-10-011-29/+12
| | | | | | Seems to be slower than memcpy + strlen. llvm-svn: 373335
* [InstCombine] sprintf(dest, "%s", str) -> memccpy(dest, str, 0, MAX)David Bolvansky2019-10-011-12/+29
| | | | llvm-svn: 373333
* DIExpression::createFragmentExpression - silence static analyzer ↵Simon Pilgrim2019-10-011-0/+1
| | | | | | DIExpression* null dereference warning with an assertion. NFCI. llvm-svn: 373326
* VirtualFileSystem - replace dyn_cast<>+assert with cast<> calls. NFCI.Simon Pilgrim2019-10-011-8/+5
| | | | | | Silences a number of clang static analyzer null dereference warnings. llvm-svn: 373325
* ObjectFile makeTriple - silence static analyzer dyn_cast<COFFObjectFile> ↵Simon Pilgrim2019-10-011-1/+1
| | | | | | | | null dereference warning. NFCI. The static analyzer is warning about a potential null dereference, but we should be able to use cast<COFFObjectFile> directly and if not assert will fire for us. llvm-svn: 373324
* InstrProf - avoid static analyzer dyn_cast<ConstantInt> null dereference ↵Simon Pilgrim2019-10-011-4/+2
| | | | | | | | | | warning. The static analyzer is warning about a potential null dereference, as we're already earlying-out for a null Constant pointer I've just folded this into a dyn_cast_or_null<ConstantInt>. No test case, this is by inspection only. llvm-svn: 373322
* ConstantFold - ConstantFoldSelectInstruction - assume constant vector ↵Simon Pilgrim2019-10-011-2/+1
| | | | | | | | elements are constant. NFCI. Goes a bit further than rL372743 which added the early out - elements should be Constant so use cast<Constant> instead (and rely on the assert if anything fails). llvm-svn: 373321
* [yaml2obj] - Allow specifying custom Link values for SHT_HASH section.George Rimar2019-10-011-1/+1
| | | | | | | | This allows setting any sh_link values for SHT_HASH sections. Differential revision: https://reviews.llvm.org/D68214 llvm-svn: 373316
* [yaml2obj/obj2yaml] - Add support for SHT_HASH sections.George Rimar2019-10-012-1/+64
| | | | | | | | | | | | | | | SHT_HASH specification is: http://www.sco.com/developers/gabi/latest/ch5.dynamic.html#hash In short the format is the following: it has 2 uint32 fields in its header: nbucket and nchain followed by (nbucket + nchain) uint32 values. This patch allows dumping and parsing such sections. Differential revision: https://reviews.llvm.org/D68085 llvm-svn: 373315
* Revert "GlobalISel: Handle llvm.read_register"Dmitri Gribenko2019-10-011-15/+0
| | | | | | | | This reverts commit r373294. It broke Clang's CodeGen/arm64-microsoft-status-reg.cpp: http://lab.llvm.org:8011/builders/clang-x86_64-debian-fast/builds/18483 llvm-svn: 373310
* [NFC][HardwareLoops] Update some iteratorsSam Parker2019-10-011-11/+6
| | | | llvm-svn: 373309
* [X86] Consider isCodeGenOnly in the EVEX2VEX pass to make VMAXPD/PS map to ↵Craig Topper2019-10-011-16/+25
| | | | | | | | | | the non-commutable VEX instruction. Use EVEX2VEX override to fix the scalar instructions. Previously the match was ambiguous and VMAXPS/PD and VMAXCPS/PD were mapped to the same VEX instruction. But we should keep the commutableness when change the opcode. llvm-svn: 373303
* [WebAssembly] Make sure EH pads are preferred in sortingHeejin Ahn2019-10-011-0/+1
| | | | | | | | | | | | | | | | | | | | | Summary: In CFGSort, we try to make EH pads have higher priorities as soon as they are ready to be sorted, to prevent creation of unwind destination mismatches in CFGStackify. We did that by making priority queues' comparison function prefer EH pads, but it was possible for an EH pad to be popped from `Preferred` queue and then not sorted immediately and enter `Ready` queue instead in a certain condition. This patch makes sure that special condition does not consider EH pads as its candidates. Reviewers: dschuff Subscribers: sbc100, jgravelle-google, hiraditya, sunfish, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68229 llvm-svn: 373302
* [WebAssembly] Unstackify regs after fixing unwinding mismatchesHeejin Ahn2019-10-012-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Fixing unwind mismatches for exception handling can result in splicing existing BBs and moving some of instructions to new BBs. In this case some of stackified def registers in the original BB can be used in the split BB. For example, we have this BB and suppose %r0 is a stackified register. ``` bb.1: %r0 = call @foo ... use %r0 ... ``` After fixing unwind mismatches in CFGStackify, `bb.1` can be split and some instructions can be moved to a newly created BB: ``` bb.1: %r0 = call @foo bb.split (new): ... use %r0 ... ``` In this case we should make %r0 un-stackified, because its use is now in another BB. When spliting a BB, this CL unstackifies all def registers that have uses in the new split BB. Reviewers: dschuff Subscribers: sbc100, jgravelle-google, hiraditya, sunfish, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68218 llvm-svn: 373301
* AMDGPU/GlobalISel: Select s1 src G_SITOFP/G_UITOFPMatt Arsenault2019-10-014-8/+55
| | | | llvm-svn: 373298
* AMDGPU/GlobalISel: Add support for init.exec intrinsicsMatt Arsenault2019-10-016-20/+42
| | | | | | | TThe existing wave32 behavior seems broken and incomplete, but this reproduces it. llvm-svn: 373296
* AMDGPU/GlobalISel: Allow scc/vcc alternative mappings for s1 constantsMatt Arsenault2019-10-011-1/+15
| | | | llvm-svn: 373295
* GlobalISel: Handle llvm.read_registerMatt Arsenault2019-10-011-0/+15
| | | | | | | | | | | | | SelectionDAG has a bunch of machinery to defer this to selection time for some reason. Just directly emit a copy during IRTranslator. The x86 usage does somewhat questionably check hasFP, which could depend on the whole function being at minimum translated. This does lose the convergent bit if the callsite had it, which may be a problem. We also lose that in general for intrinsics, which may also be a problem. llvm-svn: 373294
* AMDGPU/GlobalISel: Avoid creating shift of 0 in arg loweringMatt Arsenault2019-10-011-3/+8
| | | | | | | | This is sort of papering over the fact that we don't run a combiner anywhere, but avoiding creating 2 instructions in the first place is easy. llvm-svn: 373293
* TLI: Remove DAG argument from getRegisterByNameMatt Arsenault2019-10-0121-66/+64
| | | | | | | | | | | Replace with the MachineFunction. X86 is the only user, and only uses it for the function. This removes one obstacle from using this in GlobalISel. The other is the more tolerable EVT argument. The X86 use of the function seems questionable to me. It checks hasFP, before frame lowering. llvm-svn: 373292
* AMDGPU/GlobalISel: Select G_UADDO/G_USUBOMatt Arsenault2019-10-013-1/+47
| | | | llvm-svn: 373288
* GlobalISel: Implement widenScalar for G_SITOFP/G_UITOFP sourcesMatt Arsenault2019-10-012-7/+15
| | | | | | Legalize 16-bit G_SITOFP/G_UITOFP for AMDGPU. llvm-svn: 373287
* AMDGPU/GlobalISel: Legalize G_GLOBAL_VALUEMatt Arsenault2019-10-013-8/+105
| | | | | | | Handle other cases besides LDS. Mostly a straight port of the existing handling, without the intermediate custom nodes. llvm-svn: 373286
* DebugInfo: Add parsing support for debug_loc base address specifiersDavid Blaikie2019-10-011-3/+7
| | | | llvm-svn: 373278
* [SimplifyLibCalls] Define the value of the Euler numberEvandro Menezes2019-09-301-1/+3
| | | | | | | | | This patch fixes the build break on Windows hosts. There must be a better way of accessing the equivalent POSIX math constant `M_E`. llvm-svn: 373274
* DebugInfo: Simplify section label caching/usageDavid Blaikie2019-09-302-9/+4
| | | | llvm-svn: 373273
* [DAGCombiner] Clang format MatchRotate. NFCAmaury Sechet2019-09-301-4/+6
| | | | llvm-svn: 373269
* [globalisel][knownbits] Allow targets to call ↵Daniel Sanders2019-09-302-3/+5
| | | | | | | | | | | | | | | | | | GISelKnownBits::computeKnownBitsImpl() Summary: It seems we missed that the target hook can't query the known-bits for the inputs to a target instruction. Fix that oversight Reviewers: aditya_nandakumar Subscribers: rovka, hiraditya, volkan, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67380 llvm-svn: 373264
* [ConstantFolding] Fold constant calls to log2()Evandro Menezes2019-09-301-0/+9
| | | | | | | | Somehow, folding calls to `log2()` with a constant was missing. Differential revision: https://reviews.llvm.org/D67300 llvm-svn: 373262
* [InstCombine] Expand the simplification of log()Evandro Menezes2019-09-301-35/+153
| | | | | | | | | Expand the simplification of special cases of `log()` to include `log2()` and `log10()` as well as intrinsics and more types. Differential revision: https://reviews.llvm.org/D67199 llvm-svn: 373261
* [DAGCombiner] Update MatchRotate so that it returns an SDValue. NFCAmaury Sechet2019-09-301-22/+21
| | | | llvm-svn: 373260
* [LegacyPassManager] Deprecate the BasicBlockPass/Manager.Alina Sbirlea2019-09-303-61/+67
| | | | | | | | | | | | | | | | | Summary: The BasicBlockManager is potentially broken and should not be used. Replace all uses of the BasicBlockPass with a FunctionBlockPass+loop on blocks. Reviewers: chandlerc Subscribers: jholewinski, sanjoy.google, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68234 llvm-svn: 373254
* [FunctionAttrs] Added noalias for memccpy/mempcpy argumentsDavid Bolvansky2019-09-301-2/+11
| | | | llvm-svn: 373251
* [InstCombine][NFC] visitShl(): call SimplifyQuery::getWithInstruction() onceRoman Lebedev2019-09-301-10/+9
| | | | llvm-svn: 373249
* [X86] Mask off upper bits of splat element in LowerBUILD_VECTORvXi1 when ↵Craig Topper2019-09-301-2/+12
| | | | | | | | | | | | | | | | forming a SELECT. The i1 scalar would have been type legalized to i8, but that doesn't guarantee anything about the upper bits. If we're going to use it as condition we need to make sure the upper bits are 0. I've special cased ISD::SETCC conditions since that should guarantee zero upper bits. We could go further and use computeKnownBits, but we have no tests that would need that. Fixes PR43507. llvm-svn: 373246
* [X86] Address post-commit review from code I accidentally commited in r373136.Craig Topper2019-09-301-3/+6
| | | | | | See https://reviews.llvm.org/D68167 llvm-svn: 373245
* Revert "[MC] Emit unused undefined symbol even if its binding is not set"Nico Weber2019-09-301-0/+3
| | | | | | This reverts r373168. It caused PR43511. llvm-svn: 373242
* [PGO] Don't group COMDAT variables for compiler generated profile variables ↵Rong Xu2019-09-301-5/+1
| | | | | | | | | | | | in ELF With this patch, compiler generated profile variables will have its own COMDAT name for ELF format, which syncs the behavior with COFF. Tested with clang PGO bootstrap. This shows a modest reduction in object sizes in ELF format. Differential Revision: https://reviews.llvm.org/D68041 llvm-svn: 373241
* [NewPM] Port MachineModuleInfo to the new pass manager.Yuanfang Chen2019-09-3014-64/+110
| | | | | | | | | | | | | Existing clients are converted to use MachineModuleInfoWrapperPass. The new interface is for defining a new pass manager API in CodeGen. Reviewers: fedor.sergeev, philip.pfaffe, chandlerc, arsenm Reviewed By: arsenm, fedor.sergeev Differential Revision: https://reviews.llvm.org/D64183 llvm-svn: 373240
* [MCA] Use references to LSUnitBase in class Scheduler and add helper methods ↵Andrea Di Biagio2019-09-301-4/+4
| | | | | | to acquire/release LS queue entries. NFCI llvm-svn: 373236
* [LegacyPassManager] Attempt to fix BasicBlockManagerAlina Sbirlea2019-09-301-0/+19
| | | | | | | | | | Temporarily fix BaiscBlockManager based on the code in the other managers. Replacement of all uses of the BasicBlockPass to follow. Resolves PR42264. llvm-svn: 373235
* [X86] Add ANY_EXTEND to switch in ReplaceNodeResults, but just fall back to ↵Craig Topper2019-09-301-0/+6
| | | | | | | | | | | | | default handling. ANY_EXTEND of v8i8 is marked Custom on AVX512 for handling extends from v8i8. But the type legalization infrastructure will call ReplaceNodeResults for v8i8 results. We should just defer it the default handling instead of asserting in the default of the switch. Fixes PR43509. llvm-svn: 373234
* [AArch64][SVE] Implement punpk[hi|lo] intrinsicsKerry McLaughlin2019-09-303-4/+18
| | | | | | | | | | | | | | | | | | | | | | Summary: Adds the following two intrinsics: - int_aarch64_sve_punpkhi - int_aarch64_sve_punpklo This patch also contains a fix which allows LLVMHalfElementsVectorType to forward reference overloadable arguments. Reviewers: sdesmalen, rovka, rengolin Reviewed By: sdesmalen Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, greened, cfe-commits, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67830 llvm-svn: 373232
* [EarlyCSE] Pass preserves AA.Alina Sbirlea2019-09-301-0/+1
| | | | llvm-svn: 373231
* [InstCombine] fold negate disguised as select+mulSanjay Patel2019-09-301-0/+19
| | | | | | | | | | | | | | | | | | | | Name: negate if true %sel = select i1 %cond, i32 -1, i32 1 %r = mul i32 %sel, %x => %m = sub i32 0, %x %r = select i1 %cond, i32 %m, i32 %x Name: negate if false %sel = select i1 %cond, i32 1, i32 -1 %r = mul i32 %sel, %x => %m = sub i32 0, %x %r = select i1 %cond, i32 %x, i32 %m https://rise4fun.com/Alive/Nlh llvm-svn: 373230
* [AArch64][GlobalISel] Support lowering variadic musttail callsJessica Paquette2019-09-302-11/+91
| | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for lowering variadic musttail calls. To do this, we have to... - Detect a musttail call in a variadic function before attempting to lower the call's formal arguments. This is done in the IRTranslator. - Compute forwarded registers in `lowerFormalArguments`, and add copies for those registers. - Restore the forwarded registers in `lowerTailCall`. Because there doesn't seem to be any nice way to wrap these up into the outgoing argument handler, the restore code in `lowerTailCall` is done separately. Also, irritatingly, you have to make sure that the registers don't overlap with any passed parameters. Otherwise, the scheduler doesn't know what to do with the extra copies and asserts. Add call-translator-variadic-musttail.ll to test this. This is pretty much the same as the X86 musttail-varargs.ll test. We didn't have as nice of a test to base this off of, but the idea is the same. Differential Revision: https://reviews.llvm.org/D68043 llvm-svn: 373226
* [mips] Fix code indentation. NFCSimon Atanasyan2019-09-301-3/+3
| | | | llvm-svn: 373225
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