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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-10-01 02:07:19 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-10-01 02:07:19 +0000 |
| commit | 5823a28270e03826fc298fb80396e7c2fb37c2d7 (patch) | |
| tree | c8b43031a4b4c97a21204ad09c8dd37d8a539d09 /llvm/lib | |
| parent | bdcc6d3d2638b3a2c99ab3b9bfaa9c02e584993a (diff) | |
| download | bcm5719-llvm-5823a28270e03826fc298fb80396e7c2fb37c2d7.tar.gz bcm5719-llvm-5823a28270e03826fc298fb80396e7c2fb37c2d7.zip | |
AMDGPU/GlobalISel: Allow scc/vcc alternative mappings for s1 constants
llvm-svn: 373295
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 16 |
1 files changed, 15 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp index 82268233976..da690c37c56 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp @@ -343,7 +343,21 @@ AMDGPURegisterBankInfo::getInstrAlternativeMappings( InstructionMappings AltMappings; switch (MI.getOpcode()) { - case TargetOpcode::G_CONSTANT: + case TargetOpcode::G_CONSTANT: { + unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI); + if (Size == 1) { + static const OpRegBankEntry<1> Table[4] = { + { { AMDGPU::VGPRRegBankID }, 1 }, + { { AMDGPU::SGPRRegBankID }, 1 }, + { { AMDGPU::VCCRegBankID }, 1 }, + { { AMDGPU::SCCRegBankID }, 1 } + }; + + return addMappingFromTable<1>(MI, MRI, { 0 }, Table); + } + + LLVM_FALLTHROUGH; + } case TargetOpcode::G_FCONSTANT: case TargetOpcode::G_FRAME_INDEX: case TargetOpcode::G_GLOBAL_VALUE: { |
