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* [SelectionDAG] Add support for BITREVERSE constant foldingSimon Pilgrim2017-01-162-0/+8
| | | | | | We were relying on constant folding of the legalized instructions to do what constant folding we had previously llvm-svn: 292114
* [InstCombine][SSE] Add DemandedElts support for PSHUFB instructionsSimon Pilgrim2017-01-162-1/+21
| | | | | | | | Simplify a pshufb shuffle mask based on the elements of the mask that are actually demanded. Differential Revision: https://reviews.llvm.org/D28745 llvm-svn: 292101
* [X86] Merge the disassemblers handling of the different TYPE_RELs by getting ↵Craig Topper2017-01-162-30/+26
| | | | | | the size information from the ENCODING field. NFCI llvm-svn: 292096
* [X86] Reduce the number of operand 'types' the disassembler needs to deal ↵Craig Topper2017-01-163-102/+22
| | | | | | | | | with. NFCI We were frequently checking for a list of types and the different types conveyed no real information. So lump them together explicitly. llvm-svn: 292095
* [AVX-512] Teach the disassembler about all of the EVEX gather and scatter ↵Craig Topper2017-01-162-4/+67
| | | | | | instructions. llvm-svn: 292094
* [AVX-512] Begin giving the disassembler a way to recognize that VSIB is a ↵Craig Topper2017-01-163-0/+23
| | | | | | | | different encoding than regular addressing modes. This part first teaches it not to check error if EVEX.V2 is used by a VSIB instruction. llvm-svn: 292093
* [AVX-512] Correct memory operand size for VPGATHERQPS and VPGATHERQDCraig Topper2017-01-163-6/+11
| | | | | | | | | with ZMM index. Similar for SCATTER and the prefetch gather and scatter instructions. Fixes PR31618. llvm-svn: 292088
* [AVX-512] Fix register class in one of the gather/scatter memory operands so ↵Craig Topper2017-01-161-1/+1
| | | | | | that all 32 bit registers can be allowed. llvm-svn: 292087
* Use getLoopLatch in place of isLoopSimplifyFormXin Tong2017-01-151-4/+7
| | | | | | | | | | | | | | Summary: Use getLoopLatch in place of isLoopSimplifyForm. we do not need to know whether the loop has a preheader nor dedicated exits. Reviewers: hfinkel, sanjoy, atrick, mkuper Subscribers: mzolotukhin, llvm-commits Differential Revision: https://reviews.llvm.org/D28724 llvm-svn: 292078
* [CostModel][X86] Fix AVX512BW vector shift costs for vXi16 typesSimon Pilgrim2017-01-151-0/+8
| | | | | | We already have patterns in place to support 128/256-bit shifts without AVX512VL llvm-svn: 292077
* [InstCombine] fix formatting; NFCSanjay Patel2017-01-151-24/+22
| | | | llvm-svn: 292073
* [NVPTX] Let there be One True Way to set NVVMReflect params.Justin Lebar2017-01-152-54/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Previously there were three ways to inform the NVVMReflect pass whether you wanted to flush denormals to zero: * An LLVM command-line option * Parameters to the NVVMReflect constructor * Metadata on the module itself. This change removes the first two, leaving only the third. The motivation for this change, aside from simplifying things, is that we want LLVM to be aware of whether it's operating in FTZ mode, so other passes can use this information. Ideally we'd have a target-generic piece of metadata on the module. This change moves us in that direction. Reviewers: tra Subscribers: jholewinski, llvm-commits Differential Revision: https://reviews.llvm.org/D28700 llvm-svn: 292068
* Fix blend mask by switch the side of the operand since Blend node uses ↵Michael Zuckerman2017-01-151-2/+2
| | | | | | opposite mask then Select NODE. llvm-svn: 292066
* [InstCombine] use m_APInt to allow ashr folds for vectors with splat constantsSanjay Patel2017-01-151-3/+4
| | | | llvm-svn: 292064
* Reverted: Track validity of pass resultsSerge Pavlov2017-01-158-31/+9
| | | | | | Commits r291882 and related r291887. llvm-svn: 292062
* Revert "[GlobalISel] track predecessor mapping during switch lowering."Daniel Jasper2017-01-151-39/+16
| | | | | | | | | | This reverts commit r291973. The test fails in a Release build with LLVM_BUILD_GLOBAL_ISEL enabled. AFAICT, llc segfaults. I'll add a few more details to the original commit. llvm-svn: 292061
* NewGVN: Change a bunch of densemap find_or_creates to lookups, since they ↵Daniel Berlin2017-01-151-8/+8
| | | | | | should not be creating new entries llvm-svn: 292059
* [PM] Teach the optimization remarks emitter to handle invalidationChandler Carruth2017-01-151-0/+12
| | | | | | | | | | events. This pass sometimes has a pointer to BlockFrequencyInfo so it needs custom invalidation logic. It is also otherwise immutable so we can reduce the number of invalidations that happen substantially. llvm-svn: 292058
* [Orc][RPC] Add an RPCFunctionNotSupported error type and return it fromLang Hames2017-01-151-0/+20
| | | | | | | | | | negotiateFunction where appropriate. Replacing the old ECError with a custom type allows us to attach the name of the function that could not be negotiated, enabling better diagnostics for negotiation failures. llvm-svn: 292055
* [PM] Introduce an analysis set used to preserve all analyses overChandler Carruth2017-01-1533-50/+118
| | | | | | | | | | | | | | | a function's CFG when that CFG is unchanged. This allows transformation passes to simply claim they preserve the CFG and analysis passes to check for the CFG being preserved to remove the fanout of all analyses being listed in all passes. I've gone through and removed or cleaned up as many of the comments reminding us to do this as I could. Differential Revision: https://reviews.llvm.org/D28627 llvm-svn: 292054
* [AVX-512] Remove unnecessary duplicate broadcast patterns. NFCCraig Topper2017-01-151-6/+0
| | | | llvm-svn: 292053
* [AVX-512] Replicate some broadcast patterns to VLX and disable the AVX2 ↵Craig Topper2017-01-152-1/+8
| | | | | | patterns when VLX is available. llvm-svn: 292051
* [X86] Remove untested MOVDDUP patterns.Craig Topper2017-01-151-17/+0
| | | | | | | | These all involve bitcasts around the memory operands. This isn't something we normally do for isel patterns. I suspect DAG combine should convert the load type making this unnecessary. llvm-svn: 292050
* Give comparator const call operatorEric Fiselier2017-01-151-1/+1
| | | | llvm-svn: 292043
* PDB: Add a class to create the /names stream contents.Rui Ueyama2017-01-153-8/+105
| | | | | | | | | | This patch adds a new class NameHashTableBuilder which creates /names streams. This patch contains a test to confirm that a stream created by NameHashTableBuilder can be read by NameHashTable reader class. Differential Revision: https://reviews.llvm.org/D28707 llvm-svn: 292040
* [PM] The assumption cache is fundamentally designed to be self-updating,Chandler Carruth2017-01-152-2/+0
| | | | | | | | | | | | | | mark it as never invalidated in the new PM. The old PM already required this to work, and after a discussion with Hal this seems to really be the only sensible answer. The cache gracefully degrades as the IR is mutated, and most things which do this should already be incrementally updating the cache. This gets rid of a bunch of logic preserving and testing the invalidation of this analysis. llvm-svn: 292039
* [PM] Fix instcombine's analysis preservation in the new pass manager toChandler Carruth2017-01-141-0/+3
| | | | | | | | | | | cover domtree and alias analysis. These are the pretty clear analyses that we would always want to survive this pass. To make these survive, we also need to preserve the assumption cache. Added a test that verifies the important bits of this preservation. llvm-svn: 292037
* [InstCombine] clean up visitAshr(); NFCISanjay Patel2017-01-141-20/+9
| | | | llvm-svn: 292036
* [NewGVN] Fix a warning from GCC.Davide Italiano2017-01-141-7/+6
| | | | | | | Patch by Gonsolo. Differential Revision: https://reviews.llvm.org/D28731 llvm-svn: 292031
* [NewGVN] clang-format this file after recent changes.Davide Italiano2017-01-141-6/+7
| | | | llvm-svn: 292026
* [NewGVN] Try to be consistent wit the style used in this file. NFCI.Davide Italiano2017-01-141-1/+1
| | | | llvm-svn: 292025
* [TargetLowering] Simplfiy a bit. NFCI.Davide Italiano2017-01-141-4/+1
| | | | llvm-svn: 292024
* [CostModel][X86] Updated vXi64 ASHR costs on AVX512 targets now that D28604 ↵Simon Pilgrim2017-01-141-0/+8
| | | | | | has landed llvm-svn: 292023
* [X86][XOP] Added support for VPMADCSWD 'extend+hadd' IFMA patternsSimon Pilgrim2017-01-141-0/+3
| | | | | | VPMADCSWD act as VPADDD( VPMADDWD( x, y ), z ) - multiply+extend+hadd and add to v4i32 accumulator llvm-svn: 292021
* [X86][XOP] Added support for VPMACSDQH/VPMACSDQL 'extension' IFMA patternsSimon Pilgrim2017-01-141-1/+8
| | | | | | VPMACSDQH/VPMACSDQL act as VPADDQ( VPMULDQ( x, y ), z ) - multiply+extending either the odd/even 4i32 input elements and adding to v2i64 accumulator llvm-svn: 292020
* [X86][XOP] Added support for VPMACSWW/VPMACSDD 'lossy' IFMA patternsSimon Pilgrim2017-01-141-0/+11
| | | | | | VPMACSWW/VPMACSDD act as add( mul( x, y ), z ) - ignoring any upper bits from both the multiply and add stages llvm-svn: 292019
* [AVX-512] Teach two address instruction pass to replace masked move ↵Craig Topper2017-01-142-1/+126
| | | | | | | | | | | | instructions with blendm instructions when its beneficial. Isel now selects masked move instructions for vselect instead of blendm. But sometimes it beneficial to register allocation to remove the tied register constraint by using blendm instructions. This also picks up cases where the masked move was created due to a masked load intrinsic. Differential Revision: https://reviews.llvm.org/D28454 llvm-svn: 292005
* [AVX-512] Replace V_SET0 in AVX-512 patterns with AVX512_128_SET0. Enhance ↵Craig Topper2017-01-143-27/+46
| | | | | | | | | | AVX512_128_SET0 expansion to make this possible. We'll now expand AVX512_128_SET0 to an EVEX VXORD if VLX available. Or if its not, but register allocation has selected a non-extended register we will use VEX VXORPS. And if its an extended register without VLX we'll use a 512-bit XOR. Do the same for AVX512_FsFLD0SS/SD. This makes it possible for the register allocator to have all 32 registers available to work with. llvm-svn: 292004
* Removing potentially error-prone fallthrough. NFCMarcello Maggioni2017-01-141-0/+1
| | | | | | | | This fallthrough if other cases are added between fabs and default could cause fabs to fall to the next case resulting in a bug. Better getting rid of it immediately just to be sure. llvm-svn: 292003
* [X86] Simplify the code that calculates a scaled blend mask. We don't need a ↵Craig Topper2017-01-141-2/+1
| | | | | | second loop. llvm-svn: 291996
* [AVX-512] Change blend mask in lowerVectorShuffleAsBlend to a 64-bit value. ↵Craig Topper2017-01-141-9/+9
| | | | | | | | Also add 32-bit mode command lines to the test case that exercises this just to make sure we sanely handle the 64-bit immediate there. This fixes a undefined sanitizer failure from r291888. llvm-svn: 291994
* [Transforms/Utils] Fix some Clang-tidy modernize and Include What You Use ↵Eugene Zelenko2017-01-141-6/+15
| | | | | | warnings; other minor fixes (NFC). llvm-svn: 291983
* Compute summary before calling extractProfTotalWeightEaswaran Raman2017-01-141-11/+11
| | | | | | | | | | extractProfTotalWeight checks if the profile type is sample profile, but before that we have to ensure that summary is available. Also expanded the unittest to test the case where there is no summar Differential Revision: https://reviews.llvm.org/D28708 llvm-svn: 291982
* NewGVN: Kill unneeded DFSDomMap, cleanup a few comments.Daniel Berlin2017-01-141-13/+7
| | | | llvm-svn: 291981
* GlobalISel: Abort in ResetMachineFunctionPass if fallback isn't enabledJustin Bogner2017-01-132-5/+13
| | | | | | | | | | When GlobalISel is configured to abort rather than fallback the only thing that resetting the machine function does is make things harder to debug. If we ever get to this point in the abort configuration it indicates that we've already hit a bug, so this changes the behaviour to abort instead. llvm-svn: 291977
* [InstCombine] optimize unsigned icmp of incrementSanjay Patel2017-01-131-0/+25
| | | | | | | | | | | | | | | | | | | | | | | Allows LLVM to optimize sequences like the following: %add = add nuw i32 %x, 1 %cmp = icmp ugt i32 %add, %y Into: %cmp = icmp uge i32 %x, %y Previously, only signed comparisons were being handled. Decrements could also be handled, but 'sub nuw %x, 1' is currently canonicalized to 'add %x, -1' in InstCombineAddSub, losing the nuw flag. Removing that canonicalization seems like it might have far-reaching ramifications so I kept this simple for now. Patch by Matti Niemenmaa! Differential Revision: https://reviews.llvm.org/D24700 llvm-svn: 291975
* [GlobalISel] track predecessor mapping during switch lowering.Tim Northover2017-01-131-16/+39
| | | | | | | | Correctly populating Machine PHIs relies on knowing exactly how the IR level CFG was lowered to MachineIR. This needs to be tracked by any translation phases that meddle (currently only SwitchInst handling). llvm-svn: 291973
* [InstCombine] use m_APInt to allow lshr folds for vectors with splat constantsSanjay Patel2017-01-131-17/+14
| | | | llvm-svn: 291972
* NewGVN: Move leaders around properly to ensure we have a canonical ↵Daniel Berlin2017-01-131-40/+89
| | | | | | | | | | | | | | | | | | | | | | | | | | | | dominating leader. Fixes PR 31613. Summary: This is a testcase where phi node cycling happens, and because we do not order the leaders by domination or anything similar, the leader keeps changing. Using std::set for the members is too expensive, and we actually don't need them sorted all the time, only at leader changes. We could keep both a set and a vector, and keep them mostly sorted and resort as necessary, or use a set and a fibheap, but all of this seems premature. After running some statistics, we are able to avoid the vast majority of sorting by keeping a "next leader" field. Most congruence classes only have leader changes once or twice during GVN. Reviewers: davide Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D28594 llvm-svn: 291968
* Add a variant of DWARFDie::find() and DWARFDie::findRecursively() that takes ↵Greg Clayton2017-01-132-12/+33
| | | | | | | | | | a llvm::ArrayRef<dwarf::Attribute>. This allows us efficiently look for more than one attribute, something that is quite common in DWARF consumption. Differential Revision: https://reviews.llvm.org/D28704 llvm-svn: 291967
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