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| author | Craig Topper <craig.topper@gmail.com> | 2017-01-16 06:49:03 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@gmail.com> | 2017-01-16 06:49:03 +0000 |
| commit | ad944a1cac1476ae17c8723f3f6821a66d43fb1d (patch) | |
| tree | af38499bb042ca135d20d7599dc096a016d925a3 /llvm/lib | |
| parent | 3173a1f8ffc4a96e5389eea3175ed3a9224eb681 (diff) | |
| download | bcm5719-llvm-ad944a1cac1476ae17c8723f3f6821a66d43fb1d.tar.gz bcm5719-llvm-ad944a1cac1476ae17c8723f3f6821a66d43fb1d.zip | |
[X86] Reduce the number of operand 'types' the disassembler needs to deal with. NFCI
We were frequently checking for a list of types and the different types
conveyed no real information. So lump them together explicitly.
llvm-svn: 292095
Diffstat (limited to 'llvm/lib')
3 files changed, 22 insertions, 102 deletions
diff --git a/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp b/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp index 54fd2afd353..d5c00f584f1 100644 --- a/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp +++ b/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp @@ -392,8 +392,7 @@ static void translateImmediate(MCInst &mcInst, uint64_t immediate, } } // By default sign-extend all X86 immediates based on their encoding. - else if (type == TYPE_IMM8 || type == TYPE_IMM16 || type == TYPE_IMM32 || - type == TYPE_IMM64 || type == TYPE_IMMv) { + else if (type == TYPE_IMM) { switch (operand.encoding) { default: break; @@ -620,15 +619,13 @@ static void translateImmediate(MCInst &mcInst, uint64_t immediate, } switch (type) { - case TYPE_XMM32: - case TYPE_XMM64: - case TYPE_XMM128: + case TYPE_XMM: mcInst.addOperand(MCOperand::createReg(X86::XMM0 + (immediate >> 4))); return; - case TYPE_XMM256: + case TYPE_YMM: mcInst.addOperand(MCOperand::createReg(X86::YMM0 + (immediate >> 4))); return; - case TYPE_XMM512: + case TYPE_ZMM: mcInst.addOperand(MCOperand::createReg(X86::ZMM0 + (immediate >> 4))); return; case TYPE_BNDR: @@ -662,8 +659,7 @@ static void translateImmediate(MCInst &mcInst, uint64_t immediate, mcInst, Dis)) mcInst.addOperand(MCOperand::createImm(immediate)); - if (type == TYPE_MOFFS8 || type == TYPE_MOFFS16 || - type == TYPE_MOFFS32 || type == TYPE_MOFFS64) { + if (type == TYPE_MOFFS) { MCOperand segmentReg; segmentReg = MCOperand::createReg(segmentRegnums[insn.segmentOverride]); mcInst.addOperand(segmentReg); @@ -965,38 +961,15 @@ static bool translateRM(MCInst &mcInst, const OperandSpecifier &operand, case TYPE_R64: case TYPE_Rv: case TYPE_MM64: - case TYPE_XMM32: - case TYPE_XMM64: - case TYPE_XMM128: - case TYPE_XMM256: - case TYPE_XMM512: - case TYPE_VK1: - case TYPE_VK2: - case TYPE_VK4: - case TYPE_VK8: - case TYPE_VK16: - case TYPE_VK32: - case TYPE_VK64: + case TYPE_XMM: + case TYPE_YMM: + case TYPE_ZMM: + case TYPE_VK: case TYPE_DEBUGREG: case TYPE_CONTROLREG: case TYPE_BNDR: return translateRMRegister(mcInst, insn); case TYPE_M: - case TYPE_M8: - case TYPE_M16: - case TYPE_M32: - case TYPE_M64: - case TYPE_M128: - case TYPE_M256: - case TYPE_M512: - case TYPE_Mv: - case TYPE_M32FP: - case TYPE_M64FP: - case TYPE_M80FP: - case TYPE_M1616: - case TYPE_M1632: - case TYPE_M1664: - case TYPE_LEA: return translateRMMemory(mcInst, insn, Dis); } } diff --git a/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp b/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp index d3919d5b695..88fab4b61a9 100644 --- a/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp +++ b/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp @@ -1475,21 +1475,13 @@ static int readModRM(struct InternalInstruction* insn) { return prefix##_EAX + index; \ case TYPE_R64: \ return prefix##_RAX + index; \ - case TYPE_XMM512: \ + case TYPE_ZMM: \ return prefix##_ZMM0 + index; \ - case TYPE_XMM256: \ + case TYPE_YMM: \ return prefix##_YMM0 + index; \ - case TYPE_XMM128: \ - case TYPE_XMM64: \ - case TYPE_XMM32: \ + case TYPE_XMM: \ return prefix##_XMM0 + index; \ - case TYPE_VK1: \ - case TYPE_VK2: \ - case TYPE_VK4: \ - case TYPE_VK8: \ - case TYPE_VK16: \ - case TYPE_VK32: \ - case TYPE_VK64: \ + case TYPE_VK: \ if (index > 7) \ *valid = 0; \ return prefix##_K0 + index; \ @@ -1787,8 +1779,7 @@ static int readOperands(struct InternalInstruction* insn) { } if (readImmediate(insn, 1)) return -1; - if (Op.type == TYPE_XMM128 || - Op.type == TYPE_XMM256) + if (Op.type == TYPE_XMM || Op.type == TYPE_YMM) sawRegImm = 1; break; case ENCODING_IW: diff --git a/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h b/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h index f1db9358c00..8eca268f26c 100644 --- a/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h +++ b/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h @@ -403,81 +403,37 @@ enum OperandEncoding { ENUM_ENTRY(TYPE_REL16, "2-byte") \ ENUM_ENTRY(TYPE_REL32, "4-byte") \ ENUM_ENTRY(TYPE_REL64, "8-byte") \ - ENUM_ENTRY(TYPE_PTR1616, "2+2-byte segment+offset address") \ - ENUM_ENTRY(TYPE_PTR1632, "2+4-byte") \ - ENUM_ENTRY(TYPE_PTR1664, "2+8-byte") \ ENUM_ENTRY(TYPE_R8, "1-byte register operand") \ ENUM_ENTRY(TYPE_R16, "2-byte") \ ENUM_ENTRY(TYPE_R32, "4-byte") \ ENUM_ENTRY(TYPE_R64, "8-byte") \ - ENUM_ENTRY(TYPE_IMM8, "1-byte immediate operand") \ - ENUM_ENTRY(TYPE_IMM16, "2-byte") \ - ENUM_ENTRY(TYPE_IMM32, "4-byte") \ - ENUM_ENTRY(TYPE_IMM64, "8-byte") \ + ENUM_ENTRY(TYPE_IMM, "immediate operand") \ ENUM_ENTRY(TYPE_IMM3, "1-byte immediate operand between 0 and 7") \ ENUM_ENTRY(TYPE_IMM5, "1-byte immediate operand between 0 and 31") \ ENUM_ENTRY(TYPE_AVX512ICC, "1-byte immediate operand for AVX512 icmp") \ ENUM_ENTRY(TYPE_UIMM8, "1-byte unsigned immediate operand") \ - ENUM_ENTRY(TYPE_RM8, "1-byte register or memory operand") \ - ENUM_ENTRY(TYPE_RM16, "2-byte") \ - ENUM_ENTRY(TYPE_RM32, "4-byte") \ - ENUM_ENTRY(TYPE_RM64, "8-byte") \ ENUM_ENTRY(TYPE_M, "Memory operand") \ - ENUM_ENTRY(TYPE_M8, "1-byte") \ - ENUM_ENTRY(TYPE_M16, "2-byte") \ - ENUM_ENTRY(TYPE_M32, "4-byte") \ - ENUM_ENTRY(TYPE_M64, "8-byte") \ - ENUM_ENTRY(TYPE_LEA, "Effective address") \ - ENUM_ENTRY(TYPE_M128, "16-byte (SSE/SSE2)") \ - ENUM_ENTRY(TYPE_M256, "256-byte (AVX)") \ - ENUM_ENTRY(TYPE_M1616, "2+2-byte segment+offset address") \ - ENUM_ENTRY(TYPE_M1632, "2+4-byte") \ - ENUM_ENTRY(TYPE_M1664, "2+8-byte") \ - ENUM_ENTRY(TYPE_SRCIDX8, "1-byte memory at source index") \ - ENUM_ENTRY(TYPE_SRCIDX16, "2-byte memory at source index") \ - ENUM_ENTRY(TYPE_SRCIDX32, "4-byte memory at source index") \ - ENUM_ENTRY(TYPE_SRCIDX64, "8-byte memory at source index") \ - ENUM_ENTRY(TYPE_DSTIDX8, "1-byte memory at destination index") \ - ENUM_ENTRY(TYPE_DSTIDX16, "2-byte memory at destination index") \ - ENUM_ENTRY(TYPE_DSTIDX32, "4-byte memory at destination index") \ - ENUM_ENTRY(TYPE_DSTIDX64, "8-byte memory at destination index") \ - ENUM_ENTRY(TYPE_MOFFS8, "1-byte memory offset (relative to segment " \ - "base)") \ - ENUM_ENTRY(TYPE_MOFFS16, "2-byte") \ - ENUM_ENTRY(TYPE_MOFFS32, "4-byte") \ - ENUM_ENTRY(TYPE_MOFFS64, "8-byte") \ - ENUM_ENTRY(TYPE_M32FP, "32-bit IEE754 memory floating-point operand") \ - ENUM_ENTRY(TYPE_M64FP, "64-bit") \ - ENUM_ENTRY(TYPE_M80FP, "80-bit extended") \ + ENUM_ENTRY(TYPE_SRCIDX, "memory at source index") \ + ENUM_ENTRY(TYPE_DSTIDX, "memory at destination index") \ + ENUM_ENTRY(TYPE_MOFFS, "memory offset (relative to segment base)") \ ENUM_ENTRY(TYPE_ST, "Position on the floating-point stack") \ ENUM_ENTRY(TYPE_MM64, "8-byte MMX register") \ - ENUM_ENTRY(TYPE_XMM32, "4-byte XMM register or memory operand") \ - ENUM_ENTRY(TYPE_XMM64, "8-byte") \ - ENUM_ENTRY(TYPE_XMM128, "16-byte") \ - ENUM_ENTRY(TYPE_XMM256, "32-byte") \ - ENUM_ENTRY(TYPE_XMM512, "64-byte") \ - ENUM_ENTRY(TYPE_VK1, "1-bit") \ - ENUM_ENTRY(TYPE_VK2, "2-bit") \ - ENUM_ENTRY(TYPE_VK4, "4-bit") \ - ENUM_ENTRY(TYPE_VK8, "8-bit") \ - ENUM_ENTRY(TYPE_VK16, "16-bit") \ - ENUM_ENTRY(TYPE_VK32, "32-bit") \ - ENUM_ENTRY(TYPE_VK64, "64-bit") \ + ENUM_ENTRY(TYPE_XMM, "16-byte") \ + ENUM_ENTRY(TYPE_YMM, "32-byte") \ + ENUM_ENTRY(TYPE_ZMM, "64-byte") \ + ENUM_ENTRY(TYPE_VK, "mask register") \ ENUM_ENTRY(TYPE_SEGMENTREG, "Segment register operand") \ ENUM_ENTRY(TYPE_DEBUGREG, "Debug register operand") \ ENUM_ENTRY(TYPE_CONTROLREG, "Control register operand") \ ENUM_ENTRY(TYPE_BNDR, "MPX bounds register") \ \ - ENUM_ENTRY(TYPE_Mv, "Memory operand of operand size") \ ENUM_ENTRY(TYPE_Rv, "Register operand of operand size") \ - ENUM_ENTRY(TYPE_IMMv, "Immediate operand of operand size") \ ENUM_ENTRY(TYPE_RELv, "Immediate address of operand size") \ ENUM_ENTRY(TYPE_DUP0, "Duplicate of operand 0") \ ENUM_ENTRY(TYPE_DUP1, "operand 1") \ ENUM_ENTRY(TYPE_DUP2, "operand 2") \ ENUM_ENTRY(TYPE_DUP3, "operand 3") \ ENUM_ENTRY(TYPE_DUP4, "operand 4") \ - ENUM_ENTRY(TYPE_M512, "512-bit FPU/MMX/XMM/MXCSR state") #define ENUM_ENTRY(n, d) n, enum OperandType { |

