summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
* [ARM GlobalISel] Select G_FCONSTANT into poolsDiana Picus2019-04-101-0/+21
| | | | | | | Put all floating point constants into constant pools and load their values from there. llvm-svn: 358062
* [ARM GlobalISel] Map G_FCONSTANTDiana Picus2019-04-101-0/+8
| | | | llvm-svn: 358061
* [DebugInfo] Rename DbgValueHistoryMap::{InstrRange -> Entry}, NFCDavid Stenberg2019-04-106-63/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: In an upcoming commit the history map will be changed so that it contains explicit entries for instructions that clobber preceding debug values, rather than Begin- End range pairs, so generalize the name to "Entry". Also, prefix the iterator variable names in buildLocationList() with "E". In an upcoming commit the entry will have query functions such as "isD(e)b(u)gValue", which could at a glance make one confuse it for iterations over MachineInstrs, so make the iterator names a bit more distinct to avoid that. Reviewers: aprantl Reviewed By: aprantl Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59939 llvm-svn: 358060
* [DebugInfo] Make InstrRange into a class, NFCDavid Stenberg2019-04-104-35/+41
| | | | | | | | | | | | | | | | | | | | Summary: Replace use of std::pair by creating a class for the debug value instruction ranges instead. This is a preparatory refactoring for improving handling of clobbered fragments. In an upcoming commit the Begin pointer will become a PointerIntPair, so it will be cleaner to have a getter for that. Reviewers: aprantl Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59938 llvm-svn: 358059
* [ScheduleDAG] Add statistics for maintaining the topological order.Florian Hahn2019-04-101-0/+8
| | | | | | | | | | | | | This is helpful to measure the impact of D60125 on maintaining topological orders. Reviewers: MatzeB, atrick, efriedma, niravd Reviewed By: efriedma Differential Revision: https://reviews.llvm.org/D60187 llvm-svn: 358058
* [VPLAN] Minor improvement to testing and debug messages.Florian Hahn2019-04-101-7/+10
| | | | | | | | | | | | 1. Use computed VF for stress testing. 2. If the computed VF does not produce vector code (VF smaller than 2), force VF to be 4. 3. Test vectorization of i64 data on AArch64 to make sure we generate VF != 4 (on X86 that was already tested on AVX). Patch by Francesco Petrogalli <francesco.petrogalli@arm.com> Differential Revision: https://reviews.llvm.org/D59952 llvm-svn: 358056
* [DWARF] Simplify LineTable::findRowInSeqFangrui Song2019-04-101-35/+11
| | | | | | | | | | | | | | We want the last row whose address is less than or equal to Address. This can be computed as upper_bound - 1, which is simpler than lower_bound followed by skipping equal rows in a loop. Since FirstRow (LowPC) does not satisfy the predicate (OrderByAddress) while LastRow-1 (HighPC) satisfies the predicate. We can decrease the search range by two, i.e. upper_bound [FirstRow,LastRow) = upper_bound [FirstRow+1,LastRow-1) llvm-svn: 358053
* [InstCombine] Handle usubo always overflowNikita Popov2019-04-101-0/+3
| | | | | | | | | | | Check AlwaysOverflow condition for usubo. The implementation is the same as the existing handling for uaddo and umulo. Handling for saddo and ssubo will follow (smulo doesn't have the necessary ValueTracking support). Differential Revision: https://reviews.llvm.org/D60483 llvm-svn: 358052
* [InstCombine] Directly call computeOverflow methods in ↵Nikita Popov2019-04-101-6/+13
| | | | | | | | | OptimizeOverflowCheck; NFC Instead of using the willOverflow helpers. This makes it easier to extend handling of AlwaysOverflows. llvm-svn: 358051
* [InstCombine] Canonicalize (-X s/ Y) to -(X s/ Y).Chen Zheng2019-04-101-0/+6
| | | | | | Differential Revision: https://reviews.llvm.org/D60395 llvm-svn: 358050
* [ObjC][ARC] Convert the retainRV marker that is passed as a namedAkira Hatanaka2019-04-102-15/+8
| | | | | | | | | | | | | | | metadata into a module flag in the auto-upgrader and make the ARC contract pass read the marker as a module flag. This is needed to fix a bug where ARC contract wasn't inserting the retainRV marker when LTO was enabled, which caused objects returned from a function to be auto-released. rdar://problem/49464214 Differential Revision: https://reviews.llvm.org/D60303 llvm-svn: 358047
* [X86] Move the 2 byte VEX optimization for MOV instructions back to the ↵Craig Topper2019-04-103-54/+63
| | | | | | | | X86AsmParser::processInstruction where it used to be. Block when {vex3} prefix is present. Years ago I moved this to an InstAlias using VR128H/VR128L. But now that we support {vex3} pseudo prefix, we need to block the optimization when it is set to match gas behavior. llvm-svn: 358046
* [llvm-objdump] Don't print trailing space in dumpBytesFangrui Song2019-04-101-1/+5
| | | | | | | In disassembly output, dumpBytes prints a space, followed by a tab printed by printInstr. Remove the extra space. llvm-svn: 358045
* [Sparc] Fix incorrect MI insertion position for spilling f128.Jim Lin2019-04-101-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Obviously, new built MI (sethi+add or sethi+xor+add) for constructing large offset should be inserted before new created MI for storing even register into memory. So the insertion position should be *StMI instead of II. before fixed: std %f0, [%g1+80] sethi 4, %g1 <<< add %g1, %sp, %g1 <<< this two instructions should be put before "std %f0, [%g1+80]". sethi 4, %g1 add %g1, %sp, %g1 std %f2, [%g1+88] after fixed: sethi 4, %g1 add %g1, %sp, %g1 std %f0, [%g1+80] sethi 4, %g1 add %g1, %sp, %g1 std %f2, [%g1+88] Reviewers: venkatra, jyknight Reviewed By: jyknight Subscribers: jyknight, fedor.sergeev, jrtc27, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60397 llvm-svn: 358042
* [X86] Support the EVEX versions vcvt(t)ss2si and vcvt(t)sd2si with the ↵Craig Topper2019-04-102-32/+27
| | | | | | | | | | | | {evex} pseudo prefix in the assembler. The EVEX versions are ambiguous with the VEX versions based on operands alone so we had explicitly dropped them from the AsmMatcher table. Unfortunately, when we add them they incorrectly show in the table before their VEX counterparts. This is different how the prioritization normally works. To fix this we have to explicitly reject the instructions unless the {evex} prefix has been seen. llvm-svn: 358041
* [X86] Add VEX_LIG to scalar VEX/EVEX instructions that were missing it.Craig Topper2019-04-092-39/+40
| | | | | | | | | | Scalar VEX/EVEX instructions don't use the L bit and don't look at it for decoding either. So we should ignore it in our disassembler. The missing instructions here were found by grepping the raw tablegen class definitions in the tablegen debug output. llvm-svn: 358040
* [LLVM-C] Correct The Current Debug Location AccessorsRobert Widmann2019-04-091-1/+11
| | | | | | | | | | | | | | | | Summary: Deprecate the existing accessors for the "current debug location" of an IRBuilder. The setter could not handle being reset to NULL, and the getter would create bogus metadata if the NULL location was returned. Provide direct metadata-based accessors instead. Reviewers: whitequark, deadalnix Reviewed By: whitequark Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60484 llvm-svn: 358039
* [LLVM-C] Add Bindings to Access an Instruction's DebugLocRobert Widmann2019-04-091-0/+11
| | | | | | | | | | | | | | | | Summary: Provide direct accessors to supplement LLVMSetInstDebugLocation. In addition, properly accept and return the NULL location. The old accessors provided no way to do this, so the current debug location cannot currently be cleared. Reviewers: whitequark, deadalnix Reviewed By: whitequark Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60481 llvm-svn: 358038
* [LLVM-C] Add Section and Symbol Iterator Accessors for Object File BinariesRobert Widmann2019-04-091-0/+28
| | | | | | | | | | | | | | | | Summary: This brings us to full feature parity with the old API, so I've deprecated it and updated the tests. I'll do a follow-up patch to do some more cleanup and documentation work in this header. Reviewers: whitequark, deadalnix Reviewed By: whitequark Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60407 llvm-svn: 358037
* [X86] Fix a dangling StringRef issue introduced in r358029.Craig Topper2019-04-091-3/+4
| | | | | | | | I was attempting to convert mnemonics to lower case after processing a pseudo prefix. But the ParseOperands just hold a StringRef for tokens so there is no where to allocate the memory. Add FIXMEs for the lower case issue which also exists in the prefix parsing code. llvm-svn: 358036
* [AArch64][GlobalISel] Add isel support for vector G_ICMP and G_ASHR & G_SHLAmara Emerson2019-04-091-2/+259
| | | | | | | | | | | | | | | | The selection for G_ICMP is unfortunately not currently importable from SDAG due to the use of custom SDNodes. To support this, this selection method has an opcode table which has been generated by a script, indexed by various instruction properties. Ideally in future we will have a GISel native selection patterns that we can write in tablegen to improve on this. For selection of some types we also need support for G_ASHR and G_SHL which are generated as a result of legalization. This patch also adds support for them, generating the same code as SelectionDAG currently does. Differential Revision: https://reviews.llvm.org/D60436 llvm-svn: 358035
* [AArch64][GlobalISel] Legalize vector G_ICMP.Amara Emerson2019-04-091-2/+27
| | | | | | | | Selection support will be coming in a later patch. Differential Revision: https://reviews.llvm.org/D60435 llvm-svn: 358034
* [AArch64][GlobalISel] Add legalization for some vector G_SHL and G_ASHR.Amara Emerson2019-04-091-4/+6
| | | | | | | | This is needed for some future support for vector ICMP. Differential Revision: https://reviews.llvm.org/D60433 llvm-svn: 358033
* [GlobalISel][AArch64] Allow CallLowering to handle types which are normallyAmara Emerson2019-04-094-15/+106
| | | | | | | | | | | required to be passed as different register types. E.g. <2 x i16> may need to be passed as a larger <2 x i32> type, so formal arg lowering needs to be able truncate it back. Likewise, when dealing with returns of these types, they need to be widened in the appropriate way back. Differential Revision: https://reviews.llvm.org/D60425 llvm-svn: 358032
* [X86] Add support for {vex2}, {vex3}, and {evex} to the assembler to match ↵Craig Topper2019-04-093-9/+111
| | | | | | | | | | | | | | | | gas. Use {evex} to improve the one our 32-bit AVX512 tests. These can be used to force the encoding used for instructions. {vex2} will fail if the instruction is not VEX encoded, but otherwise won't do anything since we prefer vex2 when possible. Might need to skip use of the _REV MOV instructions for this too, but I haven't done that yet. {vex3} will force the instruction to use the 3 byte VEX encoding or fail if there is no VEX form. {evex} will force the instruction to use the EVEX version or fail if there is no EVEX version. Differential Revision: https://reviews.llvm.org/D59266 llvm-svn: 358029
* [DAGCombiner][X86][SystemZ] Canonicalize SSUBO with immediate RHS to SADDO ↵Craig Topper2019-04-091-0/+8
| | | | | | | | | | by negating the immediate. This lines up with what we do for regular subtract and it matches up better with X86 assumptions in isel patterns that add with immediate is more canonical than sub with immediate. Differential Revision: https://reviews.llvm.org/D60020 llvm-svn: 358027
* Revert "[InstCombine] [InstCombine] Canonicalize (-X s/ Y) to -(X s/ Y)."Nikita Popov2019-04-091-6/+0
| | | | | | | | | | | This reverts commit 1383a9168948aabfd827220c9445ce0ce5765800. sdiv-canonicalize.ll fails after this revision. The fold needs to be moved outside the branch handling constant operands. However when this is done there are further test changes, so I'm reverting this in the meantime. llvm-svn: 358026
* [InstCombine] Restructure OptimizeOverflowCheck; NFCNikita Popov2019-04-091-31/+28
| | | | | | | | | Change the code to always handle the unsigned+signed cases together with the same basic structure for add/sub/mul. The simple folds are always handled first and then the ValueTracking overflow checks are used. llvm-svn: 358025
* [ValueTracking] Use computeConstantRange() for signed sub overflow determinationNikita Popov2019-04-091-6/+4
| | | | | | | | | | This is the same change as D60420 but for signed sub rather than signed add: Range information is intersected into the known bits result, allows to detect more no/always overflow conditions. Differential Revision: https://reviews.llvm.org/D60469 llvm-svn: 358020
* [TargetLowering] SimplifyDemandedBits - add ISD::INSERT_SUBVECTOR supportSimon Pilgrim2019-04-091-0/+39
| | | | llvm-svn: 358019
* [InstCombine] [InstCombine] Canonicalize (-X s/ Y) to -(X s/ Y).Chen Zheng2019-04-091-0/+6
| | | | | | Differential Revision: https://reviews.llvm.org/D60395 llvm-svn: 358017
* Revert LIS handling in MachineDCEStanislav Mekhanoshin2019-04-091-28/+2
| | | | | | | | | | One of out of tree targets has regressed with this patch. Reverting it for now and let liveness to be fully reconstructed in case pass was used after the LIS is created to resolve the regression. Differential Revision: https://reviews.llvm.org/D60466 llvm-svn: 358015
* [ValueTracking] Use computeConstantRange() in signed add overflow determinationNikita Popov2019-04-091-8/+6
| | | | | | | | | | | | | This is D59386 for the signed add case. The computeConstantRange() result is now intersected into the existing known bits information, allowing to detect additional no-overflow/always-overflow conditions (though the latter isn't used yet). This (finally...) covers the motivating case from D59071. Differential Revision: https://reviews.llvm.org/D60420 llvm-svn: 358014
* [InstCombine] prevent possible miscompile with sdiv+negate of vector opSanjay Patel2019-04-091-10/+11
| | | | | | | | | | | Similar to: rL358005 Forego folding arbitrary vector constants to fix a possible miscompile bug. We can enhance the transform if we do want to handle the more complicated vector case. llvm-svn: 358013
* [DWARF] DWARFDebugLine: replace Sequence::orderByLowPC with orderByHighPCFangrui Song2019-04-091-32/+10
| | | | | | | In a sorted list of non-overlapping [LowPC,HighPC) ranges, locating an address with upper_bound on HighPC is simpler than lower_bound on LowPC. llvm-svn: 358012
* [InstCombine] prevent possible miscompile with negate+sdiv of vector opSanjay Patel2019-04-091-3/+6
| | | | | | | | | | | | | | // 0 - (X sdiv C) -> (X sdiv -C) provided the negation doesn't overflow. This fold has been around for many years and nobody noticed the potential vector miscompile from overflow until recently... So it seems unlikely that there's much demand for a vector sdiv optimization on arbitrary vector constants, so just limit the matching to splat constants to avoid the possible bug. Differential Revision: https://reviews.llvm.org/D60426 llvm-svn: 358005
* gn build: Fix Windows builds after r357797Nico Weber2019-04-091-1/+1
| | | | llvm-svn: 358004
* NFC: Refactor library-specific mappings of scalar maths functions to their ↵Nemanja Ivanovic2019-04-091-139/+4
| | | | | | | | | | | | | | | | vector counterparts This patch factors out mappings of scalar maths functions to their vector counterparts from TargetLibraryInfo.cpp to a separate VecFuncs.def file. Such mappings are currently available for Accelerate framework, and SVML library. This is in support of the follow-up: https://reviews.llvm.org/D59881 Patch by pjeeva01 Differential revision: https://reviews.llvm.org/D60211 llvm-svn: 358001
* [TargetLowering] SimplifyDemandedBits - Remove GetDemandedSrcMask lambda. NFCI.Simon Pilgrim2019-04-091-28/+21
| | | | | | An older version of this could return false but now that this always succeeds we can just inline and simplify it. llvm-svn: 357999
* Improve hashing for time profilerAnton Afanasyev2019-04-091-16/+19
| | | | | | | | | | | | | | | | Summary: Use optimized hashing while writing time trace by join two hashes to one. Used for -ftime-trace option. Reviewers: rnk, takuto.ikuta Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60404 llvm-svn: 357998
* [TargetLowering] SimplifyDemandedBits - call SimplifyDemandedBits in bitcast ↵Simon Pilgrim2019-04-091-6/+16
| | | | | | | | handling When bitcasting from a source op to a larger bitwidth op, split the demanded bits and OR them on top of one another and demand those merged bits in the SimplifyDemandedBits call on the source op. llvm-svn: 357992
* [DebugInfo] Pass all values in DebugLocEntry's constructor, NFCDavid Stenberg2019-04-092-24/+16
| | | | | | | | | | | | | | | | | | | | Summary: With MergeValues() removed, amend DebugLocEntry's constructor so that it takes multiple values rather than a single, and keep non-fragment values in OpenRanges, as this allows some cleanup of the code in buildLocationList(). Reviewers: aprantl, dblaikie, loladiro Reviewed By: aprantl Subscribers: hiraditya, llvm-commits Tags: #debug-info, #llvm Differential Revision: https://reviews.llvm.org/D59303 llvm-svn: 357988
* [PowerPC] fix trivial typos in comment, NFCHiroshi Inoue2019-04-093-6/+6
| | | | llvm-svn: 357981
* [DebugInfo] Remove redundant DebugLocEntry::MergeValues() function, NFCDavid Stenberg2019-04-092-56/+4
| | | | | | | | | | | | | | | | | | | | | | | Summary: The MergeValues() function would try to merge two entries if they shared the same beginning label. Having the same beginning label means that the former entry's range would be empty; however, after D55919 we no longer create entries for empty ranges, so we can no longer land in a situation where that check in MergeValues would succeed. Instead, the "merging" is done by keeping the live values from the preceding empty ranges in OpenRanges, and adding them to the first non-empty range. Reviewers: aprantl, dblaikie, loladiro Reviewed By: aprantl Subscribers: llvm-commits Tags: #debug-info, #llvm Differential Revision: https://reviews.llvm.org/D59301 llvm-svn: 357974
* [X86] Have EVEX2VEX tablegenerator use HasVEX_L and HasEVEX_L2 fields ↵Craig Topper2019-04-091-4/+1
| | | | | | | | | | instead of the composite EVEX_LL field. Remove the EVEX_LL field. NFCI The composite existed to simplify some other tablegen code and not really in an important way. Remove the combined field and just calculate the vector size using two ifs. llvm-svn: 357972
* [X86] Use VEX_WIG for VPINSRB/W and VPEXTRB/W to match what is done for EVEX.Craig Topper2019-04-091-5/+5
| | | | | | | | | | | | | The instruction's document this as W0 for the VEX encoding. But there's a footnote mentioning that VEX.W is ignored in 64-bit mode. And the main VEX encoding description says the VEX.W bit is ignored for instructions that are equivalent to a legacy SSE instruction that uses REX.W to select a GPR which would apply here. By making this match EVEX we can remove a special case of allowing EVEX2VEX to turn an EVEX.WIG instruction into VEX.W0. llvm-svn: 357971
* [X86] Split the VEX_WPrefix in X86Inst tablegen class into 3 separate fields ↵Craig Topper2019-04-091-8/+8
| | | | | | with clear meanings. llvm-svn: 357970
* [ValueTracking] Use ConstantRange methods; NFCNikita Popov2019-04-091-3/+3
| | | | | | | | | Switch part of the computeOverflowForSignedAdd() implementation to use Range.isAllNegative() rather than KnownBits.isNegative() and similar. They do the same thing, but using the ConstantRange methods allows dropping the KnownBits variables more easily in D60420. llvm-svn: 357969
* [ValueTracking] Explicitly specify intersection type; NFCNikita Popov2019-04-091-2/+5
| | | | | | Preparation for D60420. llvm-svn: 357968
* AMDGPU/GlobalISel: Implement call lowering for shaders returning valuesTom Stellard2019-04-091-3/+73
| | | | | | | | | | Reviewers: arsenm, nhaehnle Subscribers: kzhuravl, jvesely, wdng, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, volkan, llvm-commits Differential Revision: https://reviews.llvm.org/D57166 llvm-svn: 357964
OpenPOWER on IntegriCloud