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* [asan] cleanup: remove the SIGILL-related code (compiler part)Kostya Serebryany2012-01-061-68/+8
| | | | llvm-svn: 147667
* Fix typo in stringEli Bendersky2012-01-061-1/+1
| | | | llvm-svn: 147654
* As part of the ongoing work in finalizing the accelerator tables, extendEric Christopher2012-01-065-38/+110
| | | | | | | | | the debug type accelerator tables to contain the tag and a flag stating whether or not a compound type is a complete type. rdar://10652330 llvm-svn: 147651
* Fix SpeculativelyExecuteBB to either speculate all or none of the phisDan Gohman2012-01-051-140/+148
| | | | | | | | | | | | present in the bottom of the CFG triangle, as the transformation isn't ever valuable if the branch can't be eliminated. Also, unify some heuristics between SimplifyCFG's multiple if-converters, for consistency. This fixes rdar://10627242. llvm-svn: 147630
* PR11705, part 2: globalopt shouldn't put inttoptr/ptrtoint operations into ↵Eli Friedman2012-01-051-10/+20
| | | | | | global initializers if there's an implied extension or truncation. llvm-svn: 147625
* Link symbols with different visibilities according to the rules in theRafael Espindola2012-01-051-24/+54
| | | | | | | | System V Application Binary Interface. This lets us use -fvisibility-inlines-hidden with LTO. Fixes PR11697. llvm-svn: 147624
* Revert r56315. When the instruction to speculate is a load, thisDan Gohman2012-01-051-26/+2
| | | | | | | | code can incorrectly move the load across a store. This never happens in practice today, but only because the current heuristics accidentally preclude it. llvm-svn: 147623
* Kill ObjectCodeEmitter and BinaryObject, they were unused and superseded by MC.Benjamin Kramer2012-01-052-142/+0
| | | | llvm-svn: 147618
* SCCCaptured is trivially false on entry to this loop and not modified inside it.Nick Lewycky2012-01-051-1/+1
| | | | | | Eliminate the dead test for it on each loop iteration. No functionality change. llvm-svn: 147616
* Remove the old ELF writer.Rafael Espindola2012-01-0510-2223/+3
| | | | llvm-svn: 147615
* A small re-factored JIT/MCJIT::getPointerToNamedFunction(), so it could be ↵Danil Malyshev2012-01-053-4/+10
| | | | | | called with the base class. llvm-svn: 147610
* revert r147542 after comments from Joerg SonnenbergerSebastian Pop2012-01-054-18/+7
| | | | llvm-svn: 147608
* Remove an unused variable.Chandler Carruth2012-01-051-1/+0
| | | | llvm-svn: 147605
* Prevent a DAGCombine from firing where there are two uses ofChandler Carruth2012-01-051-1/+3
| | | | | | | | | a combined-away node and the result of the combine isn't substantially smaller than the input, it's just canonicalized. This is the first part of a significant (7%) performance gain for Snappy's hot decompression loop. llvm-svn: 147604
* Mark scalar FMA4 instructions as ignoring the VEX.L bit.Craig Topper2012-01-051-4/+4
| | | | llvm-svn: 147602
* Peephole optimization of ptest-conditioned branch in X86 arch. Performs ↵Victor Umansky2012-01-052-0/+142
| | | | | | | | | instruction combining of sequences generated by ptestz/ptestc intrinsics to ptest+jcc pair for SSE and AVX. Testing: passed 'make check' including LIT tests for all sequences being handled (both SSE and AVX) Reviewers: Evan Cheng, David Blaikie, Bruno Lopes, Elena Demikhovsky, Chad Rosier, Anton Korobeynikov llvm-svn: 147601
* Minor postra scheduler cleanup. It could result in more precise ↵Andrew Trick2012-01-051-25/+19
| | | | | | antidependence latency on ARM in exceedingly rare cases. llvm-svn: 147594
* Replace the uint64_t -> double convertion algorithm with one that's more ↵Bill Wendling2012-01-051-52/+38
| | | | | | | | | | | | | | | | | | | | | | efficient. This small bit of ASM code is sufficient to do what the old algorithm did: movq %rax, %xmm0 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U } subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 } #ifdef __SSE3__ haddpd %xmm0, %xmm0 #else pshufd $0x4e, %xmm0, %xmm1 addpd %xmm1, %xmm0 #endif It's arguably faster. One caveat, the 'haddpd' instruction isn't very fast on all processors. <rdar://problem/7719814> llvm-svn: 147593
* Reapply r146997, "Heed spill slot alignment on ARM."Jakob Stoklund Olesen2012-01-052-3/+4
| | | | | | | | | | | | Now that canRealignStack() understands frozen reserved registers, it is safe to use it for aligned spill instructions. It will only return true if the registers reserved at the beginning of register allocation allow for dynamic stack realignment. <rdar://problem/10625436> llvm-svn: 147579
* Avoid reserving an ARM base pointer during register allocation.Jakob Stoklund Olesen2012-01-051-2/+17
| | | | | | | | | | | | | | | | | Once register allocation has started the reserved registers are frozen. Fix the ARM canRealignStack() hook to respect the frozen register state. Now the hook returns false if register allocation was started with frame pointer elimination enabled. It also returns false if register allocation started without a reserved base pointer, and stack realignment would require a base pointer. This bug was breaking oggenc on armv6. No test case, an upcoming patch will use this functionality to realign the stack for spill slots when possible. llvm-svn: 147578
* Freeze reserved registers before starting register allocation.Jakob Stoklund Olesen2012-01-054-0/+7
| | | | | | | | | | | The register allocators don't currently support adding reserved registers while they are running. Extend the MRI API to keep track of the set of reserved registers when register allocation started. Target hooks like hasFP() and needsStackRealignment() can look at this set to avoid reserving more registers during register allocation. llvm-svn: 147577
* Generalize isSafeToSpeculativelyExecute to work on arbitraryDan Gohman2012-01-041-1/+5
| | | | | | | Values, rather than just Instructions, since it's interesting for ConstantExprs too. llvm-svn: 147560
* Silence warnings of a mysterious compiler that still defaults to C89.Benjamin Kramer2012-01-041-2/+2
| | | | llvm-svn: 147553
* use getHostTriple instead of getDefaultTargetTriple in getClosestTargetForJITSebastian Pop2012-01-044-7/+18
| | | | | | | | | | Get back getHostTriple. For JIT compilation, use the host triple instead of the default target: this fixes some JIT testcases that used to fail when the compiler has been configured as a cross compiler. llvm-svn: 147542
* Enable -soft-float for MIPS.Akira Hatanaka2012-01-041-7/+10
| | | | llvm-svn: 147541
* Remove pointless asserts.Nick Lewycky2012-01-041-2/+0
| | | | llvm-svn: 147529
* Teach instcombine all sorts of great stuff about shifts that have exact, nuw orNick Lewycky2012-01-042-8/+59
| | | | | | nsw bits on them. llvm-svn: 147528
* Allow vector shuffle normalizing to use concat vector even if the sources ↵Craig Topper2012-01-041-11/+24
| | | | | | are commuted in the shuffle mask. llvm-svn: 147527
* Implement VECTOR_SHUFFLE canonicalizations during DAG combine.Craig Topper2012-01-041-2/+50
| | | | llvm-svn: 147525
* Rename immLUiOpnd.Akira Hatanaka2012-01-042-3/+3
| | | | llvm-svn: 147519
* - Define base classes for Jump-and-link instructions and make 32-bit and 64-bitAkira Hatanaka2012-01-042-42/+27
| | | | | | | | | versions derive from them. - JALR64 is not needed since N64 does not emit jal. - Add template parameter to BranchLink that sets the rt field. - Fix the set of temporary registers for O32 and N64. llvm-svn: 147518
* Have getRegForInlineAsmConstraint return the correct register class when targetAkira Hatanaka2012-01-041-4/+9
| | | | | | is Mips64. llvm-svn: 147516
* Fix more places which should be checking for iOS, not darwin.Evan Cheng2012-01-043-18/+18
| | | | llvm-svn: 147513
* For x86, canonicalize maxEvan Cheng2012-01-041-0/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | (x > y) ? x : y => (x >= y) ? x : y So for something like (x - y) > 0 : (x - y) ? 0 It will be (x - y) >= 0 : (x - y) ? 0 This makes is possible to test sign-bit and eliminate a comparison against zero. e.g. subl %esi, %edi testl %edi, %edi movl $0, %eax cmovgl %edi, %eax => xorl %eax, %eax subl %esi, $edi cmovsl %eax, %edi rdar://10633221 llvm-svn: 147512
* Turn a few more inline asm errors into "emitErrors" instead of fatal errors.Chris Lattner2012-01-031-9/+21
| | | | | | | | | | | | | | | | | | Before we'd get: $ clang t.c fatal error: error in backend: Invalid operand for inline asm constraint 'i'! Now we get: $ clang t.c t.c:16:5: error: invalid operand for inline asm constraint 'i'! "movq (%4), %%mm0\n" ^ Which at least gets us the inline asm that is the problem. llvm-svn: 147502
* generalize LLVMContext::emitError to take a twine instead of a StringRef.Chris Lattner2012-01-031-3/+3
| | | | llvm-svn: 147501
* Fix 80-column violations.Chad Rosier2012-01-031-4/+5
| | | | llvm-svn: 147495
* Revert r146997, "Heed spill slot alignment on ARM."Jakob Stoklund Olesen2012-01-032-4/+3
| | | | | | | | | This patch caused a miscompilation of oggenc because a frame pointer was suddenly needed halfway through register allocation. <rdar://problem/10625436> llvm-svn: 147487
* Assert when reserved registers have been assigned.Jakob Stoklund Olesen2012-01-031-0/+4
| | | | | | | | | This can only happen if the set of reserved registers changes during register allocation. <rdar://problem/10625436> llvm-svn: 147486
* Revert 147426 because it caused pr11696.Nadav Rotem2012-01-031-18/+0
| | | | llvm-svn: 147485
* Fix incorrect widening of the bitcast sdnode in case the incoming operand is ↵Nadav Rotem2012-01-031-0/+6
| | | | | | integer-promoted. llvm-svn: 147484
* Enhance DAGCombine for transforming 128->256 casts into a vmovaps, ratherChad Rosier2012-01-032-0/+19
| | | | | | | then a vxorps + vinsertf128 pair if the original vector came from a load. rdar://10594409 llvm-svn: 147481
* Conform to the style guide; remove 'else' after 'return'. Also remove an extraNick Lewycky2012-01-031-56/+36
| | | | | | if-statement by turning it into an assert. No functionality change. llvm-svn: 147474
* Remove the restriction that target intrinsics can only involve legal types. ↵Owen Anderson2012-01-031-8/+0
| | | | | | Targets can perfects well support intrinsics on illegal types, as long as they are prepared to perform custom expansion during type legalization. For example, a target where i64 is illegal might still support the i64 intrinsic operation using pairs of i32's. ARM already does some expansions like this for non-intrinsic operations. llvm-svn: 147472
* Clarified assert text.Lang Hames2012-01-031-1/+1
| | | | llvm-svn: 147471
* Fix malformed assert.Matt Beaumont-Gay2012-01-031-1/+1
| | | | | | | | If anybody has strong feelings about 'default: assert(0 && "blah")' vs 'default: llvm_unreachable("blah")', feel free to regularize the instances of each in this file. llvm-svn: 147459
* Fix typo in ruler. No functionality change.Nick Lewycky2012-01-031-1/+1
| | | | llvm-svn: 147454
* Intel style asm variant does not need '%' prefix.Devang Patel2012-01-032-28/+28
| | | | llvm-svn: 147453
* Type: replaced usage of ID with getTypeID().Stepan Dyatkovskiy2012-01-031-11/+12
| | | | llvm-svn: 147446
* Fixed a bug in SelectionDAG.cpp.Elena Demikhovsky2012-01-031-6/+50
| | | | | | | | | | | | The failure seen on win32, when i64 type is illegal. It happens on stage of conversion VECTOR_SHUFFLE to BUILD_VECTOR. The failure message is: llc: SelectionDAG.cpp:784: void VerifyNodeCommon(llvm::SDNode*): Assertion `(I->getValueType() == EltVT || (EltVT.isInteger() && I->getValueType().isInteger() && EltVT.bitsLE(I->getValueType()))) && "Wrong operand type!"' failed. I added a special test that checks vector shuffle on win32. llvm-svn: 147445
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