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* Reorder a bunch of patterns to put the AVX version first thus giving it ↵Craig Topper2012-01-091-405/+407
| | | | | | priority over the SSE version. Another step towards trying to remove the AVX hack that disables SSE from X86Subtarget. llvm-svn: 147768
* Clean up patterns for MOVNT*. Not sure why there were floating point types ↵Craig Topper2012-01-091-17/+3
| | | | | | on MOVNTPS and MOVNTDQ. And v4i64 was completely missing. llvm-svn: 147767
* Mark MOVNTI as being supported in SSE2 OR AVX mode. This instruction has no ↵Craig Topper2012-01-091-2/+2
| | | | | | AVX equivalent so we should use the SSE version. llvm-svn: 147766
* Move SSE2 logical operations PAND/POR/PXOR/PANDN above SSE1 logical ↵Craig Topper2012-01-091-47/+63
| | | | | | operations ANDPS/ORPS/XORPS/ANDNPS. This fixes a pattern ordering issue that meant that the SSE2 instructions could never be directly selected since the SSE1 patterns would always match first. This is largely moot with the ExeDepsFix pass, but I'm trying to audit for all such ordering issues. llvm-svn: 147765
* Change some places that were checking for AVX OR SSE1/2 to use ↵Craig Topper2012-01-092-6/+6
| | | | | | hasXMM/hasXMMInt instead. Also fix one place that checked SSE3, but accidentally excluded AVX to use hasSSE3orAVX. This is a step towards removing the AVX hack from the X86Subtarget.h llvm-svn: 147764
* Don't print an unused label before .cfi_endproc.Rafael Espindola2012-01-093-7/+22
| | | | llvm-svn: 147763
* Don't disable MMX support when AVX is enabled. Fix predicates for MMX ↵Craig Topper2012-01-094-28/+52
| | | | | | instructions that were added along with SSE instructions to check for AVX in addition to SSE level. llvm-svn: 147762
* Enable FISTTP* instructions when AVX is enabled.Craig Topper2012-01-081-9/+9
| | | | llvm-svn: 147758
* Tweak my last commit to be less conservative about uses.Benjamin Kramer2012-01-081-25/+23
| | | | | | | We still save an instruction when just the "and" part is replaced. Also change the code to match comments more closely. llvm-svn: 147753
* Don't forget to transfer implicit uses of return instruction.Evan Cheng2012-01-081-2/+5
| | | | llvm-svn: 147752
* Avoid eraseing copies from a reserved register unless the definition can beEvan Cheng2012-01-081-0/+26
| | | | | | safely proven not to have been clobbered. No small test case possible. llvm-svn: 147751
* InstCombine: If we have a bit test and a sign test anded/ored together, ↵Benjamin Kramer2012-01-081-0/+32
| | | | | | | | merge the sign bit into the bit test. This is common in bit field code, e.g. checking if the first or the last bit of a bit field is set. llvm-svn: 147749
* Reverted commit #147601 upon Evan's request.Victor Umansky2012-01-082-142/+0
| | | | llvm-svn: 147748
* Remove MCELFStreamer.h.Rafael Espindola2012-01-072-143/+121
| | | | llvm-svn: 147745
* Don't print a label before .cfi_startproc when we don't need to. This makesRafael Espindola2012-01-073-9/+19
| | | | | | the produce assembly when using CFI just a bit more readable. llvm-svn: 147743
* Match SelectionDAG logic for enabling movt.Jakob Stoklund Olesen2012-01-072-2/+7
| | | | | | Darwin doesn't do static, and ELF targets only support static. llvm-svn: 147740
* Fix typo in the X86 backend readme. Patch from Jaeden Amero.Craig Topper2012-01-071-1/+1
| | | | llvm-svn: 147739
* Remove VectorExtras. This unused helper was written for a type of API that ↵Benjamin Kramer2012-01-079-9/+0
| | | | | | is discouraged now. llvm-svn: 147738
* Remove unnecessary check of hasAVX(). It's already included in hasXMM().Craig Topper2012-01-071-1/+1
| | | | llvm-svn: 147734
* Replace some uses of hasNUsesOfValue(0, X) with !hasAnyUseOfValue(X)Craig Topper2012-01-071-4/+4
| | | | llvm-svn: 147733
* Add some DAG combines for SUBC/SUBE. If nothing uses the carry/borrow out of ↵Craig Topper2012-01-071-2/+51
| | | | | | subc, turn it into a sub. Turn (subc x, x) into 0 with no borrow. Turn (subc x, 0) into x with no borrow. Turn (subc -1, x) into (xor x, -1) with no borrow. Turn sube with no borrow in into subc. llvm-svn: 147728
* Optimize reserved register coalescing.Jakob Stoklund Olesen2012-01-071-0/+25
| | | | | | | | | | | | | | | | | Reserved registers don't have proper live ranges, their LiveInterval simply has a snippet of liveness for each def. Virtual registers with a single value that is a copy of a reserved register (typically %esp) can be coalesced with the reserved register if the live range doesn't overlap any reserved register defs. When coalescing with a reserved register, don't modify the reserved register live range. Just leave it as a bunch of dead defs. This eliminates quadratic coalescer behavior in i386 functions with many function calls. PR11699 llvm-svn: 147726
* Use the 'regalloc' debug tag for most register allocator tracing.Jakob Stoklund Olesen2012-01-073-3/+3
| | | | llvm-svn: 147725
* Enable redundant phi elimination after LSR.Andrew Trick2012-01-071-1/+3
| | | | | | This will be more important as we extend the LSR pass in ways that don't rely on the formula solver. In particular, we need it for constructing IV chains. llvm-svn: 147724
* Use getRegForValue() to materialize the address of ARM globals.Jakob Stoklund Olesen2012-01-071-10/+0
| | | | | | | | | This enables basic local CSE, giving us 20% smaller code for consumer-typeset in -O0 builds. <rdar://problem/10658692> llvm-svn: 147720
* Revert part of r147716. Looks like x87 instructions kill markers are all messedEvan Cheng2012-01-071-9/+11
| | | | | | | | | | up so branch folding pass can't use the scavenger. :-( This doesn't breaks anything currently. It just means targets which do not carefully update kill markers cannot run post-ra scheduler (not new, it has always been the case). We should fix this at some point since it's really hacky. llvm-svn: 147719
* LSR: Don't optimize loops if an outer loop has no preheader.Andrew Trick2012-01-071-1/+8
| | | | | | | | LoopSimplify may not run on some outer loops, e.g. because of indirect branches. SCEVExpander simply cannot handle outer loops with no preheaders. Fixes rdar://10655343 SCEVExpander segfault. llvm-svn: 147718
* Split Finish into Finish and FinishImpl to have a common place to do end ofRafael Espindola2012-01-0711-21/+28
| | | | | | | | file error checking. Use that to error on an unfinished cfi_startproc. The error is not nice, but is already better than a segmentation fault. llvm-svn: 147717
* Added a late machine instruction copy propagation pass. This catchesEvan Cheng2012-01-079-38/+274
| | | | | | | | | | | | | | | | | | | | | | | | opportunities that only present themselves after late optimizations such as tail duplication .e.g. ## BB#1: movl %eax, %ecx movl %ecx, %eax ret The register allocator also leaves some of them around (due to false dep between copies from phi-elimination, etc.) This required some changes in codegen passes. Post-ra scheduler and the pseudo-instruction expansion passes have been moved after branch folding and tail merging. They were before branch folding before because it did not always update block livein's. That's fixed now. The pass change makes independently since we want to properly schedule instructions after branch folding / tail duplication. rdar://10428165 rdar://10640363 llvm-svn: 147716
* Copy implicit defs (e.g. r0) when changing tBX_RET to tPOP_RET. This bug isEvan Cheng2012-01-071-0/+1
| | | | | | | exposed with an upcoming change will would delete the copy to return register because there is no use! It's amazing anything works. llvm-svn: 147715
* Use movw+movt in ARMFastISel::ARMMaterializeGV.Jakob Stoklund Olesen2012-01-071-29/+50
| | | | | | | | | | | | | This eliminates a lot of constant pool entries for -O0 builds of code with many global variable accesses. This speeds up -O0 codegen of consumer-typeset by 2x because the constant island pass no longer has to look at thousands of constant pool entries. <rdar://problem/10629774> llvm-svn: 147712
* LSR: run DeleteDeadPhis before replaceCongruentPhis.Andrew Trick2012-01-071-19/+15
| | | | llvm-svn: 147711
* Cleanup comments and argument types related to my previous ↵Andrew Trick2012-01-071-4/+5
| | | | | | replaceCongruentPhis checkin. llvm-svn: 147709
* Extended replaceCongruentPhis to handle mixed phi types.Andrew Trick2012-01-072-15/+63
| | | | llvm-svn: 147707
* Make the 'x' constraint work for AVX registers as well.Eric Christopher2012-01-071-3/+13
| | | | | | Fixes rdar://10614894 llvm-svn: 147704
* Missing raw_ostream.h breaks MSVC build.Andrew Trick2012-01-071-0/+1
| | | | llvm-svn: 147703
* Expose isNonConstantNegative to users of ScalarEvolution.Andrew Trick2012-01-072-20/+20
| | | | llvm-svn: 147700
* Add comment.Chad Rosier2012-01-061-0/+4
| | | | llvm-svn: 147696
* Add a comment and ensure that anyone else looking at this code doesn't startEric Christopher2012-01-061-6/+5
| | | | | | to bleed from the eyes. llvm-svn: 147695
* Use const vector references instead of a vector copy. Spotted by Devang.Eric Christopher2012-01-061-4/+4
| | | | llvm-svn: 147694
* Use -> instead of (*iter).Eric Christopher2012-01-061-10/+10
| | | | llvm-svn: 147693
* Enable aligned NEON spilling by default.Jakob Stoklund Olesen2012-01-061-1/+1
| | | | | | Experiments show this to be a small speedup for modern ARM cores. llvm-svn: 147689
* Put all IVUsers in the processed set. Allow querying IVUsers with ↵Andrew Trick2012-01-061-3/+6
| | | | | | isIVUserOrOperand. llvm-svn: 147686
* Abort AdjustBBOffsetsAfter early when possible.Jakob Stoklund Olesen2012-01-061-2/+10
| | | | llvm-svn: 147685
* SCEVExpander: hoistStep should check strict dominance.Andrew Trick2012-01-061-1/+1
| | | | llvm-svn: 147683
* Tracing to help investigate issues with SjLj spill code.Andrew Trick2012-01-061-0/+2
| | | | llvm-svn: 147682
* Initializing to false makes better sense. Thanks, David.Chad Rosier2012-01-061-1/+1
| | | | llvm-svn: 147679
* Fix uninitialized variable warning.Chad Rosier2012-01-061-1/+1
| | | | llvm-svn: 147676
* Fix uninitialized variable warning.Chad Rosier2012-01-061-1/+1
| | | | llvm-svn: 147675
* Fix a leak I noticed while reviewing the accelerator table changes. PassesEric Christopher2012-01-061-0/+5
| | | | | | | | lldb testsuite. rdar://10652330 llvm-svn: 147673
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