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* X86: Remove implicit ilist iterator conversions, NFCDuncan P. N. Exon Smith2015-10-198-31/+24
| | | | llvm-svn: 250741
* [RuntimeDyld][COFF] Fix some endianness issues, re-enable the regression test.Lang Hames2015-10-191-10/+7
| | | | llvm-svn: 250733
* Restore the original behavior of SelectionDAG::getTargetIndex().Owen Anderson2015-10-191-1/+1
| | | | | | It looks like an extra negation snuck in as apart of restoring it. llvm-svn: 250726
* [Hexagon] Remove unnecessary argument sign extendsKrzysztof Parzyszek2015-10-193-0/+155
| | | | llvm-svn: 250724
* Pass FunctionInfoIndex by reference to WriteFunctionSummaryToFile (NFC)Teresa Johnson2015-10-191-8/+8
| | | | | | Implemented suggestion by dblakie in review for r250704. llvm-svn: 250723
* Add missing override noticed by Clang's -Winconsistent-missing-override.Benjamin Kramer2015-10-191-1/+1
| | | | llvm-svn: 250720
* [AArch64]Merge halfword loads into a 32-bit loadJun Bum Lim2015-10-191-45/+215
| | | | | | | | | | | | | Convert two halfword loads into a single 32-bit word load with bitfield extract instructions. For example : ldrh w0, [x2] ldrh w1, [x2, #2] becomes ldr w0, [x2] ubfx w1, w0, #16, #16 and w0, w0, #ffff llvm-svn: 250719
* [Hexagon] Fix debug information for local objectsKrzysztof Parzyszek2015-10-194-117/+170
| | | | | | | | | | | | - Isolate the check for the existence of a stack frame into hasFP. - Implement getFrameIndexReference for DWARF address computation. - Use getFrameIndexReference for offset computation in eliminateFrameIndex. - Preserve debug information for dynamically allocated stack objects. - Prefer FP to access local objects at -O0. - Add experimental code to skip allocframe when not strictly necessary (disabled by default). llvm-svn: 250718
* Put back SelectionDAG::getTargetIndex.Benjamin Kramer2015-10-191-0/+18
| | | | | | | While technically this is untested dead code, it has out-of-tree users. This reverts a part of r250434. llvm-svn: 250717
* [Hexagon] Delay emission of CFI instructionsKrzysztof Parzyszek2015-10-193-98/+178
| | | | | | | Emit the CFI instructions after all code transformation have been done. This will avoid any interference between CFI instructions and packetization. llvm-svn: 250714
* Revert "RegisterPressure: allocatable physreg uses are always kills"Matthias Braun2015-10-191-27/+25
| | | | | | | | | This reverts commit r250596. Reverted for now as the commit triggers assert in the AMDGPU target pending investigation. llvm-svn: 250713
* [Orc] Add support for emitting indirect stubs directly into the JIT target'sLang Hames2015-10-192-6/+87
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | memory, rather than representing the stubs in IR. Update the CompileOnDemand layer to use this functionality. Directly emitting stubs is much cheaper than building them in IR and codegen'ing them (see below). It also plays well with remote JITing - stubs can be emitted directly in the target process, rather than having to send them over the wire. The downsides are: (1) Care must be taken when resolving symbols, as stub symbols are held in a separate symbol table. This is only a problem for layer writers and other people using this API directly. The CompileOnDemand layer hides this detail. (2) Aliases of function stubs can't be symbolic any more (since there's no symbol definition in IR), but must be converted into a constant pointer expression. This means that modules containing aliases of stubs cannot be cached. In practice this is unlikely to be a problem: There's no benefit to caching such a module anyway. On balance I think the extra performance is more than worth the trade-offs: In a simple stress test with 10000 dummy functions requiring stubs and a single executed "hello world" main function, directly emitting stubs reduced user time for JITing / executing by over 90% (1.5s for IR stubs vs 0.1s for direct emission). llvm-svn: 250712
* Remove CRLF newlines. NFC.Benjamin Kramer2015-10-191-6/+6
| | | | llvm-svn: 250698
* Fix mapping of @llvm.arm.ssat/usat intrinsics to ssat/usat instructionsAsiri Rathnayake2015-10-191-4/+4
| | | | | | | | | | | | | The mapping of these two intrinsics in ARMInstrInfo.td had a small omission which lead to their operands not being validated/transformed before being lowered into usat and ssat instructions. This can cause incorrect instructions to be emitted. I've also added tests for the remaining two saturating arithmatic intrinsics @llvm.arm.qadd and @llvm.arm.qsub as they are missing codegen tests. llvm-svn: 250697
* [GlobalsAA] Fix a really horrible iterator invalidation bugJames Molloy2015-10-191-1/+4
| | | | | | | | | | We were keeping a reference to an object in a DenseMap then mutating it. At the end of the function we were attempting to clone that reference into other keys in the DenseMap, but DenseMap may well decide to resize its hashtable which would invalidate the reference! It took an extremely complex testcase to catch this - many thanks to Zhendong Su for catching it in PR25225. This fixes PR25225. llvm-svn: 250692
* Removed parameter "Consecutive" from isLegalMaskedLoad() / isLegalMaskedStore().Elena Demikhovsky2015-10-195-24/+19
| | | | | | | | | | Originally I planned to use the same interface for masked gather/scatter and set isConsecutive to "false" in this case. Now I'm implementing masked gather/scatter and see that the interface is inconvenient. I want to add interfaces isLegalMaskedGather() / isLegalMaskedScatter() instead of using the "Consecutive" parameter in the existing interfaces. Differential Revision: http://reviews.llvm.org/D13850 llvm-svn: 250686
* [mips][microMIPS] Implement ADDQ.PH, ADDQ_S.W, ADDQH.PH, ADDQH.W, ADDSC, ↵Zlatko Buljan2015-10-193-21/+62
| | | | | | | | ADDU.PH, ADDU_S.QB, ADDWC and ADDUH.QB instructions Differential Revision: http://reviews.llvm.org/D13130 llvm-svn: 250685
* [mips][microMIPS] Implement ABSQ.QB, ABSQ_S.PH, ABSQ_S.W, ABSQ_S.QB, INSV, ↵Zlatko Buljan2015-10-193-10/+76
| | | | | | | | MADD, MADDU, MSUB, MSUBU, MULT and MULTU instructions Differential Revision: http://reviews.llvm.org/D13721 llvm-svn: 250683
* [PGO] Eliminate prof data register calls on FreeBSD platformXinliang David Li2015-10-191-1/+3
| | | | | | | This is a follow up patch of r250199 after verifying the start/stop section symbols work as spected on FreeBSD. llvm-svn: 250679
* Preserve CFG in MergedLoadStoreMotion. This fixes PR24426.Jakub Staszak2015-10-181-0/+1
| | | | llvm-svn: 250660
* Use SDValue bool check. NFCI.Simon Pilgrim2015-10-181-2/+2
| | | | llvm-svn: 250653
* Move one-use variable inside test. NFC.Simon Pilgrim2015-10-181-2/+1
| | | | llvm-svn: 250651
* [X86][AVX512DQ] add scalar fpclassAsaf Badouh2015-10-184-6/+61
| | | | | | Differential Revision: http://reviews.llvm.org/D13769 llvm-svn: 250650
* AVX512: Lowering i8/i16 vector CTLZ using the dword LZCNT vector instructionIgor Breger2015-10-182-23/+123
| | | | | | Differential Revision: http://reviews.llvm.org/D13632 llvm-svn: 250649
* [Sparc] Use MCPhysReg instead of unsigned to size static arrays of ↵Craig Topper2015-10-181-6/+7
| | | | | | registers. Should reduce the table size. llvm-svn: 250644
* Use array_lengthof. NFCCraig Topper2015-10-181-1/+1
| | | | llvm-svn: 250643
* Make a bunch of static arrays const.Craig Topper2015-10-1815-41/+48
| | | | llvm-svn: 250642
* [RuntimeDyld] Add support for absolute symbols.Lang Hames2015-10-183-18/+42
| | | | llvm-svn: 250639
* Minor Instr PGO code restructuringXinliang David Li2015-10-183-115/+42
| | | | | | | | | | | | | | | | 1. Key constant values (version, magic) and data structures related to raw and indexed profile format are moved into one centralized file: InstrProf.h. 2. Utility function such as MD5Hash computation is also moved to the common header to allow sharing with other components in the future. 3. A header data structure is introduced for Indexed format so that the reader and writer can always be in sync. 4. Added some comments to document different places where multiple definition of the data structure must be kept in sync (reader/writer, runtime, lowering etc). No functional change is intended. Differential Revision: http://reviews.llvm.org/D13758 llvm-svn: 250638
* [SCEV] Fix whitespace issues and remove extra braces; NFCSanjoy Das2015-10-181-10/+7
| | | | llvm-svn: 250636
* [SCEV] Use std::all_of and std::any_of; NFCSanjoy Das2015-10-181-16/+11
| | | | llvm-svn: 250635
* [SCEV] Use auto where it helps remove line breaks; NFCSanjoy Das2015-10-181-13/+6
| | | | llvm-svn: 250634
* [SCEV] Use range for loops; NFCSanjoy Das2015-10-181-22/+17
| | | | llvm-svn: 250633
* Use std::find instead of manual loop.Craig Topper2015-10-171-5/+2
| | | | llvm-svn: 250624
* Use std::is_sorted to replace a custom version. Also replace a comparison ↵Craig Topper2015-10-172-16/+4
| | | | | | predicate struct with a lambda. llvm-svn: 250623
* [X86][XOP] Add VPROT instruction opcodesSimon Pilgrim2015-10-175-33/+32
| | | | | | Added X86ISD opcodes for VPROT vector rotate by variable and by immediate. llvm-svn: 250620
* Remove unnecessary 'const' pointed out by David Blaikie.Craig Topper2015-10-171-2/+2
| | | | llvm-svn: 250619
* [DAG] Ensure vector constant folding uses correct scalar undef typesSimon Pilgrim2015-10-171-2/+2
| | | | | | Minor fix to D13665 found during post-commit review. llvm-svn: 250616
* Replace a custom table sort check with std::is_sorted. Change a function to ↵Craig Topper2015-10-171-17/+8
| | | | | | take ArrayRef instead of pointer and length. NFC llvm-svn: 250615
* Use std::begin/end and std::is_sorted to simplify some code. NFCCraig Topper2015-10-172-15/+11
| | | | llvm-svn: 250614
* [CostModel] Fixed AVX integer shift costsSimon Pilgrim2015-10-171-12/+36
| | | | | | Targets with AVX but without AVX2 were incorrectly reporting costs of 256-bit integer shifts. llvm-svn: 250611
* [X86][FastISel] Teach how to select SSE4A nontemporal stores.Simon Pilgrim2015-10-171-4/+15
| | | | | | | | | | Add FastISel support for SSE4A scalar float / double non-temporal stores Follow up to D13698 Differential Revision: http://reviews.llvm.org/D13773 llvm-svn: 250610
* [InstCombine] SSE4A constant folding and conversion to shuffles.Simon Pilgrim2015-10-171-53/+270
| | | | | | | | | | | | | This patch improves support for combining the SSE4A EXTRQ(I) and INSERTQ(I) intrinsics: 1 - Converts INSERTQ/EXTRQ calls to INSERTQI/EXTRQI if the 'bit index' and 'length' operands are constant 2 - Converts INSERTQI/EXTRQI calls to shufflevector if the bit index/length are both byte aligned (we can already lower shuffles to INSERTQI/EXTRQI if its useful) 3 - Constant folding support 4 - Add zeroinitializer handling Differential Revision: http://reviews.llvm.org/D13348 llvm-svn: 250609
* [libFuzzer] add -shuffle flagKostya Serebryany2015-10-174-5/+10
| | | | llvm-svn: 250603
* [Hexagon] Adding skeleton of HVX extension instructions.Colin LeMahieu2015-10-1717-13/+4259
| | | | llvm-svn: 250600
* RegisterPressure: Unify the sparse sets in LiveRegsSet; NFCMatthias Braun2015-10-171-12/+19
| | | | | | Also do some cleanups comment improvements. llvm-svn: 250598
* RegisterPressure: allocatable physreg uses are always killsMatthias Braun2015-10-171-25/+27
| | | | | | | | | | | | | | This property was already used in the code path when no liveness intervals are present. Unfortunately the code path that uses liveness intervals tried to query a cached live interval for an allocatable physreg, those are usually not computed so a conservative default was used. This doesn't affect any of the lit testcases. This is a foreclosure to upcoming changes which should be NFC but without this patch this tidbit wouldn't be NFC. llvm-svn: 250596
* RegisterPressure: Remove 0 entries from PressureChangeMatthias Braun2015-10-171-4/+14
| | | | | | | | | | | This should not change behaviour because as far as I can see all code reading the pressure changes has no effect if the PressureInc is 0. Removing these entries however does avoid unnecessary computation, and results in a more stable debug output. I want the stable debug output to check that some upcoming changes are indeed NFC and identical even at the debug output level. llvm-svn: 250595
* WebAssembly: don't omit dead vregs from localsJF Bastien2015-10-171-2/+4
| | | | | | | | | | | | | | | | | | Summary: This is a temporary hack until we get around to remapping the vreg numbers to local numbers. Dead vregs cause bad numbering and make consumers sad. We could also just look at debug info an use named locals instead, but vregs have to work properly anyways so there! Reviewers: binji, sunfish Subscribers: jfb, llvm-commits, dschuff Differential Revision: http://reviews.llvm.org/D13839 llvm-svn: 250594
* WebAssembly: fix the syntax for comparisonsJF Bastien2015-10-171-8/+8
| | | | | | | | | | | | Summary: It has also slightly changed. Reviewers: binji Subscribers: jfb, dschuff, llvm-commits, sunfish Differential Revision: http://reviews.llvm.org/D13837 llvm-svn: 250591
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