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* Simplify the DenseSet used for hashing CodeView records.Zachary Turner2017-11-301-96/+44
| | | | | | | | | | | | | | This was storing the hash alongside the key so that the hash doesn't need to be re-computed every time, but in doing so it was allocating a structure to keep the key size small in the DenseMap. This is a noble goal, but it also leads to a pointer indirection on every probe, and this cost of this pointer indirection ends up being higher than the cost of having a slightly larger entry in the hash table. Removing this not only simplifies the code, but yields a small but noticeable performance improvement in the type merging algorithm. llvm-svn: 319493
* AMDGPU: Use gfx9 carry-less add/sub instructionsMatt Arsenault2017-11-306-34/+118
| | | | llvm-svn: 319491
* XOR the frame pointer with the stack cookie when protecting the stackReid Kleckner2017-11-306-5/+55
| | | | | | | | | | | | Summary: This strengthens the guard and matches MSVC. Reviewers: hans, etienneb Subscribers: hiraditya, JDevlieghere, vlad.tsyrklevich, llvm-commits Differential Revision: https://reviews.llvm.org/D40622 llvm-svn: 319490
* Add visibility flag to Wasm symbol flagsSam Clegg2017-11-303-4/+13
| | | | | | | | | | | | | | The LLVM "hidden" flag needs to be passed through the Wasm intermediate objects in order for the linker to apply it to the final Wasm object. The corresponding change in LLD is here: https://github.com/WebAssembly/lld/pull/14 Patch by Nicholas Wilson Differential Revision: https://reviews.llvm.org/D40442 llvm-svn: 319488
* [memcpyopt] Teach memcpyopt to optimize across basic blocksDan Gohman2017-11-302-3/+36
| | | | | | | | | | | | This teaches memcpyopt to make a non-local memdep query when a local query indicates that the dependency is non-local. This notably allows it to eliminate many more llvm.memcpy calls in common Rust code, often by 20-30%. Fixes PR28958. Differential Revision: https://reviews.llvm.org/D38374 llvm-svn: 319482
* [InlineCost] Prefer getFunction() to two calls to getParent().Davide Italiano2017-11-301-3/+3
| | | | | | Improves clarity, also slightly cheaper. NFCI. llvm-svn: 319481
* [Hexagon] Implement HexagonSubtarget::useAA()Krzysztof Parzyszek2017-11-302-1/+14
| | | | llvm-svn: 319477
* [globalisel][tablegen] Add support for relative AtomicOrderingsDaniel Sanders2017-11-301-18/+16
| | | | | | | No test yet because the relevant rules are blocked on the atomic_load, and atomic_store nodes. llvm-svn: 319475
* [Hexagon] Solo instructions cannot be used with new value jumpsKrzysztof Parzyszek2017-11-301-0/+3
| | | | llvm-svn: 319470
* [X86] Promote i8 CTPOP to i32 instead of i16 when we have the POPCNT ↵Craig Topper2017-11-301-1/+1
| | | | | | | | instruction. The 32-bit version is shorter to encode and the zext we emit for the promotion is likely going to be a 32-bit zero extend anyway. llvm-svn: 319468
* [aarch64][globalisel] Legalize G_ATOMIC_CMPXCHG_WITH_SUCCESS and G_ATOMICRMW_*Daniel Sanders2017-11-303-1/+40
| | | | | | | | | | | G_ATOMICRMW_* is generally legal on AArch64. The exception is G_ATOMICRMW_NAND. G_ATOMIC_CMPXCHG_WITH_SUCCESS needs to be lowered to G_ATOMIC_CMPXCHG with an external comparison. Note that IRTranslator doesn't generate these instructions yet. llvm-svn: 319466
* [GlobalISel][IRTranslator] Fix crash during translation of zero sized ↵Amara Emerson2017-11-302-1/+14
| | | | | | | | | | | | loads/stores/args/returns. This fixes PR35358. rdar://35619533 Differential Revision: https://reviews.llvm.org/D40604 llvm-svn: 319465
* [PGO] Skip counter promotion for infinite loopsXinliang David Li2017-11-301-0/+3
| | | | | | Differential Revision: http://reviews.llvm.org/D40662 llvm-svn: 319462
* Split TypeTableBuilder into two classes.Zachary Turner2017-11-306-58/+154
| | | | llvm-svn: 319456
* [WebAssembly] Revert r319186 "Support bitcasted function addresses with ↵Dan Gohman2017-11-301-0/+5
| | | | | | | | | | | varargs." The patch broke Emscripten's EM_ASM macros, which utiltize unprototyped functions. See https://bugs.llvm.org/show_bug.cgi?id=35385 for details. llvm-svn: 319452
* [CodeGen] Always use `printReg` to print registers in both MIR and debugFrancis Visoiu Mistrih2017-11-3016-90/+80
| | | | | | | | | | | | | | output As part of the unification of the debug format and the MIR format, always use `printReg` to print all kinds of registers. Updated the tests using '_' instead of '%noreg' until we decide which one we want to be the default one. Differential Revision: https://reviews.llvm.org/D40421 llvm-svn: 319445
* [FuzzMutate] Bailout from injecting into empty basic blocks.Igor Laevsky2017-11-301-0/+2
| | | | | | | | | | In rare cases we can receive request to inject into completelly empty basic block. In the normal case all basic blocks contain at least terminator instruction, but it is possible that the only instruction is catchpad instruction which is not part of the instruction iterator. This case seems rare enough to not care about it. Submiting without review, since it seems almost NFC. I couldn't come up with any reasonable way to test this. llvm-svn: 319444
* [FuzzMutate] Correctly handle vector types in the insertvalue operationIgor Laevsky2017-11-301-4/+6
| | | | | | Differential Revision: https://reviews.llvm.org/D40397 llvm-svn: 319442
* [FuzzMutate] Don't use index operands as sinksIgor Laevsky2017-11-301-2/+3
| | | | | | Differential Revision: https://reviews.llvm.org/D40396 llvm-svn: 319441
* [FuzzMutate] Pick correct index for the insertvalue instructionIgor Laevsky2017-11-301-3/+3
| | | | | | Differential Revision: https://reviews.llvm.org/D40395 llvm-svn: 319440
* [FuzzMutate] Don't create load as a new source if it doesn't match with the ↵Igor Laevsky2017-11-301-11/+14
| | | | | | | | descriptor Differential Revision: https://reviews.llvm.org/D40394 llvm-svn: 319439
* [FuzzMutate] Don't crash when we can't remove instruction from empty functionIgor Laevsky2017-11-301-1/+3
| | | | | | Differential Revision: https://reviews.llvm.org/D40393 llvm-svn: 319438
* [PowerPC] Recommit r314244 with refactoring and off by defaultNemanja Ivanovic2017-11-301-0/+1236
| | | | | | | | | | | | | | | This re-commits everything that was pulled in r314244. The transformation is off by default (patch to enable it to follow). The code is refactored to have a single entry-point and provide fine-grained control over patterns that it selects. This patch also fixes the bugs in the original code. Everything that failed with the original patch has been re-tested with this patch (with the transformation turned on). So the patch to turn this on is soon to follow. Differential Revision: https://reviews.llvm.org/D38575 llvm-svn: 319434
* [X86][AVX512] Tag fcmp/ptest/ternlog instructions scheduler classesSimon Pilgrim2017-11-301-70/+90
| | | | llvm-svn: 319433
* [MC] Function stack size section.Sean Eveson2017-11-302-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | Re applying after fixing issues in the diff, sorry for any painful conflicts/merges! Original RFC: http://lists.llvm.org/pipermail/llvm-dev/2017-August/117028.html This change adds a '.stack-size' section containing metadata on function stack sizes to output ELF files behind the new -stack-size-section flag. The section contains pairs of function symbol references (8 byte) and stack sizes (unsigned LEB128). The contents of this section can be used to measure changes to stack sizes between different versions of the compiler or a source base. The advantage of having a section is that we can extract this information when examining binaries that we didn't build, and it allows users and tools easy access to that information just by referencing the binary. There is a follow up change to add an option to clang. Thanks. Reviewers: hfinkel, MatzeB Reviewed By: MatzeB Subscribers: thegameg, asb, llvm-commits Differential Revision: https://reviews.llvm.org/D39788 llvm-svn: 319430
* Revert r319423: [MC] Function stack size section.Sean Eveson2017-11-302-935/+905
| | | | | | I messed up the diff. llvm-svn: 319429
* [ARM GlobalISel] Bail out for byvalDiana Picus2017-11-301-1/+7
| | | | | | | Fallback if we have a byval parameter or argument since we don't support them yet. llvm-svn: 319428
* [CodeGen] Print "%vreg0" as "%0" in both MIR and debug outputFrancis Visoiu Mistrih2017-11-3035-303/+303
| | | | | | | | | | | | | | | | | As part of the unification of the debug format and the MIR format, avoid printing "vreg" for virtual registers (which is one of the current MIR possibilities). Basically: * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E "s/%vreg([0-9]+)/%\1/g" * grep -nr '%vreg' . and fix if needed * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E "s/ vreg([0-9]+)/ %\1/g" * grep -nr 'vreg[0-9]\+' . and fix if needed Differential Revision: https://reviews.llvm.org/D40420 llvm-svn: 319427
* [X86][AVX512] Tag binop/rounding/sae instructions scheduler classesSimon Pilgrim2017-11-301-124/+143
| | | | llvm-svn: 319424
* [MC] Function stack size section.Sean Eveson2017-11-302-905/+935
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: Original RFC: http://lists.llvm.org/pipermail/llvm-dev/2017-August/117028.html I wasn't sure who to put as reviewers, so please add/remove people as appropriate. This change adds a '.stack-size' section containing metadata on function stack sizes to output ELF files behind the new -stack-size-section flag. The section contains pairs of function symbol references (8 byte) and stack sizes (unsigned LEB128). The contents of this section can be used to measure changes to stack sizes between different versions of the compiler or a source base. The advantage of having a section is that we can extract this information when examining binaries that we didn't build, and it allows users and tools easy access to that information just by referencing the binary. There is a follow up change to add an option to clang. Thanks. Reviewers: hfinkel, MatzeB Reviewed By: MatzeB Subscribers: thegameg, asb, llvm-commits Differential Revision: https://reviews.llvm.org/D39788 llvm-svn: 319423
* [DAGCombine] Refactor ReduceLoadWidthSam Parker2017-11-301-50/+33
| | | | | | | | | | visitAND attempts to narrow the width of extending loads that are then masked off. ReduceLoadWidth already exists for a similar purpose and handles shifts, so I've moved the code to handle AND nodes there. Differential Revision: https://reviews.llvm.org/D39595 llvm-svn: 319421
* Support generic lowering of vector bswapSerge Guelton2017-11-301-10/+10
| | | | llvm-svn: 319419
* [X86][AVX512] Tag RCP/RSQRT/GETEXP instructions scheduler classesSimon Pilgrim2017-11-302-64/+100
| | | | llvm-svn: 319418
* Revert rL319407: [SROA] enable splitting for non-whole-alloca loads and stores Hiroshi Inoue2017-11-301-21/+10
| | | | | | This reverts commit rL319407 due to failures in some buildbot. llvm-svn: 319410
* [SystemZ] Bugfix in adjustSubwordCmp.Jonas Paulsson2017-11-301-4/+11
| | | | | | | | | | | | | | | | Csmith generated a program where a store after load to the same address did not get chained after the new load created during DAG legalizing, and so performed an illegal overwrite of the expected value. When the new zero-extending load is created, the chain users of the original load must be updated, which was not done previously. A similar case was also found and handled in lowerBITCAST. Review: Ulrich Weigand https://reviews.llvm.org/D40542 llvm-svn: 319409
* [SROA] enable splitting for non-whole-alloca loads and storesHiroshi Inoue2017-11-301-10/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, SROA splits loads and stores only when they are accessing the whole alloca. This patch relaxes this limitation to allow splitting a load/store if all other loads and stores to the alloca are disjoint to or fully included in the current load/store. If there is no other load or store that crosses the boundary of the current load/store, the current splitting implementation works as is. The whole-alloca loads and stores meet this new condition and so they are still splittable. Here is a simplified motivating example. struct record { long long a; int b; int c; }; int func(struct record r) { for (int i = 0; i < r.c; i++) r.b++; return r.b; } When updating r.b (or r.c as well), LLVM generates redundant instructions on some platforms (such as x86_64, ppc64); here, r.b and r.c are packed into one 64-bit GPR when the struct is passed as a method argument. With this patch, the above example is compiled into only few instructions without loop. Without the patch, unnecessary loop-carried dependency is introduced by SROA and the loop cannot be eliminated by the later optimizers. Differential Revision: https://reviews.llvm.org/D32998 llvm-svn: 319407
* [X86] Optimize avx2 vgatherqps for v2f32 with v2i64 index type.Craig Topper2017-11-301-7/+12
| | | | | | Normal type legalization will widen everything. This requires forcing 0s into the mask register. We can instead choose the form that only reads 2 elements without zeroing the mask. llvm-svn: 319406
* [X86] Make sure we don't remove sign extends of masks with AVX2 masked gathers.Craig Topper2017-11-301-3/+4
| | | | | | We don't use k-registers and instead use the MSB so we need to make sure we sign extend the mask to the msb. llvm-svn: 319405
* - Removed unused lamba (IsReturnBlock) causing build bots to fail for r319398Graham Yiu2017-11-301-7/+1
| | | | | | - Added lit testcases that were supposed to be part of r319398 llvm-svn: 319399
* With PGO information, we can do more aggressive outlining of cold regions in ↵Graham Yiu2017-11-301-88/+579
| | | | | | | | | | | | the inline candidate function. This contrasts with the scheme of keeping only the 'early return' portion of the inline candidate and outlining the rest of the function as a single function call. Support for outlining multiple regions of each function is added, as well as some basic heuristics to determine which regions are good to outline. Outline candidates limited to regions that are single-entry & single-exit. We also avoid outlining regions that produce live-exit variables, which may inhibit some forms of code motion (like commoning). Fallback to the regular partial inlining scheme is retained when either i) no regions are identified for outlining in the function, or ii) the outlined function could not be inlined in any of its callers. Differential Revision: https://reviews.llvm.org/D38190 llvm-svn: 319398
* AMDGPU: Allow negative MUBUF vaddr for gfx9Matt Arsenault2017-11-302-4/+21
| | | | | | | | GFX9 does not enable bounds checking for the resource descriptors used for private access, so it should be OK to use vaddr with a potentially negative value. llvm-svn: 319393
* [Coverage] Use the most-recent completed region count (PR35437)Vedant Kumar2017-11-301-0/+6
| | | | | | | | | | | | | | | This is a fix for the coverage segment builder. If multiple regions must be popped off the active stack at once, and more than one of them end at the same location, emit a segment using the count from the most-recent completed region. Fixes PR35437, rdar://35760630 Testing: invoked llvm-cov on a stage2 build of clang, additional unit tests, check-profile llvm-svn: 319391
* LowerTypeTests: Deduplicate code. NFC.Peter Collingbourne2017-11-301-30/+17
| | | | llvm-svn: 319390
* LowerTypeTests: Remove unnecessary cast. NFC.Peter Collingbourne2017-11-301-1/+1
| | | | llvm-svn: 319387
* [X86] Remove some questionable looking code that seems to be looking through ↵Craig Topper2017-11-291-1/+1
| | | | | | | | | | a VZEXT to create a larger VSEXT. If the input the vzext was signed this would do the wrong thing. Not sure how to test this. llvm-svn: 319382
* First step towards more human-friendly PPC assembler output:Joerg Sonnenberger2017-11-293-32/+74
| | | | | | | | | | | | | | - add -ppc-reg-with-percent-prefix option to use %r3 etc as register names - split off logic for Darwinish verbose conditional codes into a helper function - be explicit about Darwin vs AIX vs GNUish assembler flavors Based on the patch from Alexandre Yukio Yamashita Differential Revision: https://reviews.llvm.org/D39016 llvm-svn: 319381
* [WebAssembly] Update test expectations for gcc torture testsSam Clegg2017-11-291-6/+0
| | | | | | | | | I believe these were recently fixed by: https://reviews.llvm.org/rL319186 Differential Revision: https://reviews.llvm.org/D40619 llvm-svn: 319380
* [CodeView] Factor some code out of TypeTableBuilder.Zachary Turner2017-11-292-38/+36
| | | | | | | | | | | This class had some code that would automatically remap type indices before hashing and serializing. The only caller of this method was the TypeStreamMerger anyway, and the method doesn't make general sense, and prevents making certain future improvements to the class. So, factoring this up one level into the TypeStreamMerger where it belongs. llvm-svn: 319377
* [SelectionDAG][X86] Teach promotion legalization for fp_to_sint/fp_to_uint ↵Craig Topper2017-11-291-3/+11
| | | | | | | | | | | | to insert an assertsext/assertzext based on the original type If we put in an assertsext/zext here, we're able to generate better truncate code using pack on pre-avx512 targets. Similar is already done during type legalization. This is the equivalent for op legalization Differential Revision: https://reviews.llvm.org/D40591 llvm-svn: 319368
* [WebAssembly] Fix fptoui lowering boundsDan Gohman2017-11-292-14/+47
| | | | | | | To fully avoid trapping on wasm, fptoui needs a second check to ensure that the operand isn't below the supported range. llvm-svn: 319354
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